From: kan.liang@linux.intel.com
To: mingo@kernel.org, acme@redhat.com, peterz@infradead.org,
vincent.weaver@maine.edu, linux-kernel@vger.kernel.org
Cc: alexander.shishkin@linux.intel.com, ak@linux.intel.com,
jolsa@redhat.com, eranian@google.com,
Kan Liang <kan.liang@linux.intel.com>
Subject: [PATCH V3 4/5] perf/x86: Clean up pebs_no_xmm_regs
Date: Tue, 28 May 2019 15:08:33 -0700 [thread overview]
Message-ID: <1559081314-9714-4-git-send-email-kan.liang@linux.intel.com> (raw)
In-Reply-To: <1559081314-9714-1-git-send-email-kan.liang@linux.intel.com>
From: Kan Liang <kan.liang@linux.intel.com>
Don't need pebs_no_xmm_regs anymore. The capabilities
PERF_PMU_CAP_EXTENDED_REGS can be used to check if XMM registers
collection is supported.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
New for V3
arch/x86/events/core.c | 2 +-
arch/x86/events/intel/ds.c | 6 ++----
arch/x86/events/perf_event.h | 3 +--
3 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 7708a6f..52a9746 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -568,7 +568,7 @@ int x86_pmu_hw_config(struct perf_event *event)
* be collected in PEBS on some platforms, e.g. Icelake
*/
if (unlikely(event->attr.sample_regs_intr & PERF_REG_EXTENDED_MASK)) {
- if (x86_pmu.pebs_no_xmm_regs)
+ if (!(event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS))
return -EINVAL;
if (!event->attr.precise_ip)
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index e6a0fa9..53f9dc5 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -1964,10 +1964,9 @@ void __init intel_ds_init(void)
x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
- if (x86_pmu.version <= 4) {
+ if (x86_pmu.version <= 4)
x86_pmu.pebs_no_isolation = 1;
- x86_pmu.pebs_no_xmm_regs = 1;
- }
+
if (x86_pmu.pebs) {
char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
char *pebs_qual = "";
@@ -2023,7 +2022,6 @@ void __init intel_ds_init(void)
x86_get_pmu()->capabilities |= PERF_PMU_CAP_EXTENDED_REGS;
} else {
/* Only basic record supported */
- x86_pmu.pebs_no_xmm_regs = 1;
x86_pmu.large_pebs_flags &=
~(PERF_SAMPLE_ADDR |
PERF_SAMPLE_TIME |
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index d3b6e90..4e34685 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -650,8 +650,7 @@ struct x86_pmu {
pebs_broken :1,
pebs_prec_dist :1,
pebs_no_tlb :1,
- pebs_no_isolation :1,
- pebs_no_xmm_regs :1;
+ pebs_no_isolation :1;
int pebs_record_size;
int pebs_buffer_size;
int max_pebs_events;
--
2.7.4
next prev parent reply other threads:[~2019-05-28 22:09 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-28 22:08 [PATCH V3 1/5] perf: Disable extended registers for non-support PMUs kan.liang
2019-05-28 22:08 ` [PATCH V3 2/5] perf/x86/regs: Check reserved bits kan.liang
2019-06-25 8:20 ` [tip:perf/urgent] " tip-bot for Kan Liang
2019-05-28 22:08 ` [PATCH V3 3/5] perf/x86: Clean up PEBS_XMM_REGS kan.liang
2019-06-25 8:21 ` [tip:perf/urgent] " tip-bot for Kan Liang
2019-05-28 22:08 ` kan.liang [this message]
2019-06-25 8:22 ` [tip:perf/urgent] perf/x86: Remove pmu->pebs_no_xmm_regs tip-bot for Kan Liang
2019-05-28 22:08 ` [PATCH V3 5/5] perf regs x86: Use PERF_REG_EXTENDED_MASK kan.liang
2019-06-25 8:22 ` [tip:perf/urgent] perf/x86/regs: " tip-bot for Kan Liang
2019-06-20 12:24 ` [PATCH V3 1/5] perf: Disable extended registers for non-support PMUs Peter Zijlstra
2019-06-25 8:19 ` [tip:perf/urgent] perf/x86: Disable extended registers for non-supported PMUs tip-bot for Kan Liang
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