From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
To: stefan.wahren@i2se.com, Eric Anholt <eric@anholt.net>,
Florian Fainelli <f.fainelli@gmail.com>,
Ray Jui <rjui@broadcom.com>,
Scott Branden <sbranden@broadcom.com>,
bcm-kernel-feedback-list@broadcom.com
Cc: mbrugger@suse.de, viresh.kumar@linaro.org, rjw@rjwysocki.net,
sboyd@kernel.org, ptesarik@suse.com,
linux-rpi-kernel@lists.infradead.org, ssuloev@orpaltech.com,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
mturquette@baylibre.com, linux-pm@vger.kernel.org,
Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
linux-kernel@vger.kernel.org
Subject: [PATCH 1/4] clk: bcm2835: remove pllb
Date: Tue, 4 Jun 2019 19:32:20 +0200 [thread overview]
Message-ID: <20190604173223.4229-2-nsaenzjulienne@suse.de> (raw)
In-Reply-To: <20190604173223.4229-1-nsaenzjulienne@suse.de>
Raspberry Pi's firmware controls this pll, we should use the firmware
interface to access it.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
---
drivers/clk/bcm/clk-bcm2835.c | 25 -------------------------
1 file changed, 25 deletions(-)
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 770bb01f523e..ccb0319fc2e9 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -1651,31 +1651,6 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
.fixed_divider = 1,
.flags = CLK_SET_RATE_PARENT),
- /* PLLB is used for the ARM's clock. */
- [BCM2835_PLLB] = REGISTER_PLL(
- .name = "pllb",
- .cm_ctrl_reg = CM_PLLB,
- .a2w_ctrl_reg = A2W_PLLB_CTRL,
- .frac_reg = A2W_PLLB_FRAC,
- .ana_reg_base = A2W_PLLB_ANA0,
- .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
- .lock_mask = CM_LOCK_FLOCKB,
-
- .ana = &bcm2835_ana_default,
-
- .min_rate = 600000000u,
- .max_rate = 3000000000u,
- .max_fb_rate = BCM2835_MAX_FB_RATE),
- [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV(
- .name = "pllb_arm",
- .source_pll = "pllb",
- .cm_reg = CM_PLLB,
- .a2w_reg = A2W_PLLB_ARM,
- .load_mask = CM_PLLB_LOADARM,
- .hold_mask = CM_PLLB_HOLDARM,
- .fixed_divider = 1,
- .flags = CLK_SET_RATE_PARENT),
-
/*
* PLLC is the core PLL, used to drive the core VPU clock.
*
--
2.21.0
next prev parent reply other threads:[~2019-06-04 17:33 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-04 17:32 [PATCH 0/4] cpufreq support for the Raspberry Pi Nicolas Saenz Julienne
2019-06-04 17:32 ` Nicolas Saenz Julienne [this message]
2019-06-05 0:03 ` [PATCH 1/4] clk: bcm2835: remove pllb Eric Anholt
2019-06-05 10:49 ` Stefan Wahren
2019-06-04 17:32 ` [PATCH 2/4] clk: bcm283x: add driver interfacing with Raspberry Pi's firmware Nicolas Saenz Julienne
2019-06-05 10:44 ` Stefan Wahren
2019-06-05 12:23 ` Nicolas Saenz Julienne
2019-06-04 17:32 ` [PATCH 3/4] clk: bcm2835: register Raspberry Pi's firmware clk device Nicolas Saenz Julienne
2019-06-05 0:00 ` Eric Anholt
2019-06-05 9:11 ` Nicolas Saenz Julienne
2019-06-05 10:01 ` Stefan Wahren
2019-06-04 17:32 ` [PATCH 4/4] cpufreq: add driver for Raspbery Pi Nicolas Saenz Julienne
2019-06-05 0:18 ` Eric Anholt
2019-06-05 9:12 ` Nicolas Saenz Julienne
2019-06-05 11:15 ` Stefan Wahren
2019-06-05 9:46 ` [PATCH 0/4] cpufreq support for the Raspberry Pi Stefan Wahren
2019-06-05 11:00 ` Nicolas Saenz Julienne
2019-06-05 11:34 ` Stefan Wahren
2019-06-05 12:27 ` Nicolas Saenz Julienne
2019-06-05 13:12 ` Stefan Wahren
2019-06-05 19:11 ` Nicolas Saenz Julienne
2019-06-05 20:15 ` Stefan Wahren
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