From: "Z.q. Hou" <zhiqiang.hou@nxp.com>
To: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"arnd@arndb.de" <arnd@arndb.de>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
"l.subrahmanya@mobiveil.co.in" <l.subrahmanya@mobiveil.co.in>,
"shawnguo@kernel.org" <shawnguo@kernel.org>,
"m.karthikeyan@mobiveil.co.in" <m.karthikeyan@mobiveil.co.in>,
Leo Li <leoyang.li@nxp.com>,
"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
"will.deacon@arm.com" <will.deacon@arm.com>
Cc: Mingkai Hu <mingkai.hu@nxp.com>,
"M.h. Lian" <minghuan.lian@nxp.com>,
Xiaowei Bao <xiaowei.bao@nxp.com>,
"Z.q. Hou" <zhiqiang.hou@nxp.com>
Subject: [PATCHv7 4/7] PCI: mobiveil: Add 8-bit and 16-bit CSR register accessors
Date: Tue, 25 Jun 2019 09:09:28 +0000 [thread overview]
Message-ID: <20190625091039.18933-5-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <20190625091039.18933-1-Zhiqiang.Hou@nxp.com>
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
There are some 8-bit and 16-bit registers in PCIe configuration
space, so add these accessors accordingly.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
---
V7:
- New patch moved from the fixes series.
.../pci/controller/mobiveil/pcie-mobiveil.h | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
index 159b0142a2bc..a729a4f879fe 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
@@ -185,9 +185,29 @@ static inline u32 csr_readl(struct mobiveil_pcie *pcie, u32 off)
return csr_read(pcie, off, 0x4);
}
+static inline u32 csr_readw(struct mobiveil_pcie *pcie, u32 off)
+{
+ return csr_read(pcie, off, 0x2);
+}
+
+static inline u32 csr_readb(struct mobiveil_pcie *pcie, u32 off)
+{
+ return csr_read(pcie, off, 0x1);
+}
+
static inline void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
{
csr_write(pcie, val, off, 0x4);
}
+static inline void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32 off)
+{
+ csr_write(pcie, val, off, 0x2);
+}
+
+static inline void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off)
+{
+ csr_write(pcie, val, off, 0x1);
+}
+
#endif /* _PCIE_MOBIVEIL_H */
--
2.17.1
next prev parent reply other threads:[~2019-06-25 9:09 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-25 9:09 [PATCHv7 0/7] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Z.q. Hou
2019-06-25 9:09 ` [PATCHv7 1/7] PCI: mobiveil: Refactor Mobiveil PCIe Host Bridge IP driver Z.q. Hou
2019-06-25 9:09 ` [PATCHv7 2/7] PCI: mobiveil: Make mobiveil_host_init() can be used to re-init host Z.q. Hou
2019-06-25 9:09 ` [PATCHv7 3/7] dt-bindings: PCI: Add NXP Layerscape SoCs PCIe Gen4 controller Z.q. Hou
2019-06-25 9:09 ` Z.q. Hou [this message]
2019-06-25 9:09 ` [PATCHv7 5/7] PCI: mobiveil: Add PCIe Gen4 RC driver for NXP Layerscape SoCs Z.q. Hou
2019-06-25 9:09 ` [PATCHv7 6/7] arm64: dts: lx2160a: Add PCIe controller DT nodes Z.q. Hou
2019-06-25 9:09 ` [PATCHv7 7/7] arm64: defconfig: Enable CONFIG_PCIE_LAYERSCAPE_GEN4 Z.q. Hou
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