From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Robin Murphy <robin.murphy@arm.com>,
Rob Herring <robh+dt@kernel.org>
Cc: Evan Green <evgreen@chromium.org>, Tomasz Figa <tfiga@google.com>,
Will Deacon <will.deacon@arm.com>,
<linux-mediatek@lists.infradead.org>,
<srv_heupstream@mediatek.com>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<iommu@lists.linux-foundation.org>, <yingjoe.chen@mediatek.com>,
<yong.wu@mediatek.com>, <youlin.pei@mediatek.com>,
Nicolas Boichat <drinkcat@chromium.org>, <anan.sun@mediatek.com>,
Matthias Kaehlcke <mka@chromium.org>
Subject: [PATCH v8 11/21] iommu/mediatek: Move reset_axi into plat_data
Date: Sat, 29 Jun 2019 10:39:45 +0800 [thread overview]
Message-ID: <1561775995-24963-12-git-send-email-yong.wu@mediatek.com> (raw)
In-Reply-To: <1561775995-24963-11-git-send-email-yong.wu@mediatek.com>
In mt8173 and mt8183, 0x48 is REG_MMU_STANDARD_AXI_MODE while it is
REG_MMU_CTRL in the other SoCs, and the bits meaning is completely
different with the REG_MMU_STANDARD_AXI_MODE.
This patch moves this property to plat_data, it's also a preparing
patch for mt8183.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
---
drivers/iommu/mtk_iommu.c | 4 ++--
drivers/iommu/mtk_iommu.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 4f8a2cb..1f9f307 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -575,8 +575,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
}
writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
- /* It's MISC control register whose default value is ok except mt8173.*/
- if (data->plat_data->m4u_plat == M4U_MT8173)
+ if (data->plat_data->reset_axi)
writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE);
if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
@@ -772,6 +771,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
.m4u_plat = M4U_MT8173,
.has_4gb_mode = true,
.has_bclk = true,
+ .reset_axi = true,
.larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */
};
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 61fd5d6..55d73c1 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -46,7 +46,7 @@ struct mtk_iommu_plat_data {
/* HW will use the EMI clock if there isn't the "bclk". */
bool has_bclk;
-
+ bool reset_axi;
unsigned char larbid_remap[MTK_LARB_NR_MAX];
};
--
1.9.1
next prev parent reply other threads:[~2019-06-29 2:41 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-29 2:39 [PATCH v8 10/21] iommu/mediatek: Refine protect memory definition Yong Wu
2019-06-29 2:39 ` Yong Wu [this message]
2019-06-29 2:39 ` [PATCH v8 12/21] iommu/mediatek: Move vld_pa_rng into plat_data Yong Wu
2019-06-29 2:39 ` [PATCH v8 13/21] memory: mtk-smi: Add gals support Yong Wu
2019-06-29 2:39 ` [PATCH v8 14/21] iommu/mediatek: Add mt8183 IOMMU support Yong Wu
2019-06-29 2:39 ` [PATCH v8 15/21] iommu/mediatek: Add mmu1 support Yong Wu
2019-06-29 2:39 ` [PATCH v8 16/21] memory: mtk-smi: Invoke pm runtime_callback to enable clocks Yong Wu
2019-06-29 2:39 ` [PATCH v8 17/21] memory: mtk-smi: Add bus_sel for mt8183 Yong Wu
2019-06-29 2:39 ` [PATCH v8 18/21] iommu/mediatek: Fix VLD_PA_RNG register backup when suspend Yong Wu
2019-06-29 2:39 ` [PATCH v8 19/21] memory: mtk-smi: Get rid of need_larbid Yong Wu
2019-06-29 2:39 ` [PATCH v8 20/21] iommu/mediatek: Clean up struct mtk_smi_iommu Yong Wu
2019-06-29 2:39 ` [PATCH v8 21/21] iommu/mediatek: Switch to SPDX license identifier Yong Wu
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