From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com,
l.subrahmanya@mobiveil.co.in, shawnguo@kernel.org,
leoyang.li@nxp.com, lorenzo.pieralisi@arm.com,
catalin.marinas@arm.com, will.deacon@arm.com
Cc: Mingkai.Hu@nxp.com, Minghuan.Lian@nxp.com, Xiaowei.Bao@nxp.com,
Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Subject: [PATCHv6 14/28] PCI: mobiveil: Make the register updating more readable
Date: Fri, 5 Jul 2019 17:56:42 +0800 [thread overview]
Message-ID: <20190705095656.19191-15-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <20190705095656.19191-1-Zhiqiang.Hou@nxp.com>
To make the register updating more readable, outstand the fields
to update by changing the register updating sequence to:
a. Read out the original value from the target register.
b. Update the value in one sentence.
c. Program the updated value back to the register.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
V6:
- Splited from #2 of v5 patches, no functional change.
drivers/pci/controller/pcie-mobiveil.c | 43 ++++++++++++++++++-------------
1 files changed, 25 insertions(+), 18 deletions(-)
diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index 0767f19..906299b 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -299,6 +299,7 @@ static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
unsigned int devfn, int where)
{
struct mobiveil_pcie *pcie = bus->sysdata;
+ u32 value;
if (!mobiveil_pcie_valid_device(bus, devfn))
return NULL;
@@ -313,10 +314,12 @@ static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
* (BDF) in PAB_AXI_AMAP_PEX_WIN_L0 Register.
* Relies on pci_lock serialization
*/
- csr_writel(pcie, bus->number << PAB_BUS_SHIFT |
- PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
- PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT,
- PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
+ value = bus->number << PAB_BUS_SHIFT |
+ PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
+ PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT;
+
+ csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
+
return pcie->config_axi_slave_base + where;
}
@@ -463,19 +466,20 @@ static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
}
pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
- csr_writel(pcie, pio_ctrl_val | (1 << PIO_ENABLE_SHIFT),
- PAB_PEX_PIO_CTRL);
- amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
- amap_ctrl_dw = (amap_ctrl_dw | (type << AMAP_CTRL_TYPE_SHIFT));
- amap_ctrl_dw = (amap_ctrl_dw | (1 << AMAP_CTRL_EN_SHIFT));
+ pio_ctrl_val |= 1 << PIO_ENABLE_SHIFT;
+ csr_writel(pcie, pio_ctrl_val, PAB_PEX_PIO_CTRL);
- csr_writel(pcie, amap_ctrl_dw | lower_32_bits(size64),
- PAB_PEX_AMAP_CTRL(win_num));
+ amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
+ amap_ctrl_dw |= (type << AMAP_CTRL_TYPE_SHIFT) |
+ (1 << AMAP_CTRL_EN_SHIFT) |
+ lower_32_bits(size64);
+ csr_writel(pcie, amap_ctrl_dw, PAB_PEX_AMAP_CTRL(win_num));
csr_writel(pcie, upper_32_bits(size64),
PAB_EXT_PEX_AMAP_SIZEN(win_num));
csr_writel(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));
+
csr_writel(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num));
csr_writel(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num));
}
@@ -575,16 +579,16 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
* Space
*/
value = csr_readl(pcie, PCI_COMMAND);
- csr_writel(pcie, value | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER, PCI_COMMAND);
+ value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+ csr_writel(pcie, value, PCI_COMMAND);
/*
* program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL
* register
*/
pab_ctrl = csr_readl(pcie, PAB_CTRL);
- csr_writel(pcie, pab_ctrl | (1 << AMBA_PIO_ENABLE_SHIFT) |
- (1 << PEX_PIO_ENABLE_SHIFT), PAB_CTRL);
+ pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT);
+ csr_writel(pcie, pab_ctrl, PAB_CTRL);
csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
PAB_INTP_AMBA_MISC_ENB);
@@ -594,7 +598,8 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
* PAB_AXI_PIO_CTRL Register
*/
value = csr_readl(pcie, PAB_AXI_PIO_CTRL);
- csr_writel(pcie, value | APIO_EN_MASK, PAB_AXI_PIO_CTRL);
+ value |= APIO_EN_MASK;
+ csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
/*
* we'll program one outbound window for config reads and
@@ -649,7 +654,8 @@ static void mobiveil_mask_intx_irq(struct irq_data *data)
mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
- csr_writel(pcie, (shifted_val & (~mask)), PAB_INTP_AMBA_MISC_ENB);
+ shifted_val &= ~mask;
+ csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
}
@@ -664,7 +670,8 @@ static void mobiveil_unmask_intx_irq(struct irq_data *data)
mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
- csr_writel(pcie, (shifted_val | mask), PAB_INTP_AMBA_MISC_ENB);
+ shifted_val |= mask;
+ csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
}
--
1.7.1
next prev parent reply other threads:[~2019-07-05 10:08 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-05 9:56 [PATCHv6 00/28] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 01/28] PCI: mobiveil: Unify register accessors Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 02/28] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 03/28] PCI: mobiveil: Fix PCI base address in MEM/IO outbound windows Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 04/28] PCI: mobiveil: Update the resource list traversal function Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 05/28] PCI: mobiveil: Use WIN_NUM_0 explicitly for CFG outbound window Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 06/28] PCI: mobiveil: Use the 1st inbound window for MEM inbound transactions Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 07/28] PCI: mobiveil: Fix the Class Code field Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 08/28] PCI: mobiveil: Move the link up waiting out of mobiveil_host_init() Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 09/28] PCI: mobiveil: Move IRQ chained handler setup out of DT parse Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 10/28] PCI: mobiveil: Initialize Primary/Secondary/Subordinate bus numbers Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 11/28] PCI: mobiveil: Fix devfn check in mobiveil_pcie_valid_device() Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 12/28] dt-bindings: PCI: mobiveil: Change gpio_slave and apb_csr to optional Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 13/28] PCI: mobiveil: Reformat the code for readability Hou Zhiqiang
2019-07-05 9:56 ` Hou Zhiqiang [this message]
2019-07-05 9:56 ` [PATCHv6 15/28] PCI: mobiveil: Revise the MEM/IO outbound window initialization Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 16/28] PCI: mobiveil: Fix the returned error number Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 17/28] PCI: mobiveil: Remove an unnecessary return value check Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 18/28] PCI: mobiveil: Remove redundant var definitions and register read operations Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 19/28] PCI: mobiveil: Fix the valid check for inbound and outbound window Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 20/28] PCI: mobiveil: Add the statistic of initialized inbound windows Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 21/28] PCI: mobiveil: Clear the target fields before updating the register Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 22/28] PCI: mobiveil: Mask out the lower 10-bit hardcode window size Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 23/28] PCI: mobiveil: Add upper 32-bit CPU base address setup in outbound window Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 24/28] PCI: mobiveil: Add upper 32-bit PCI base address setup in inbound window Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 25/28] PCI: mobiveil: Fix the CPU " Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 26/28] PCI: mobiveil: Move PCIe PIO enablement out of inbound window routine Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 27/28] PCI: mobiveil: Fix infinite-loop in the INTx process Hou Zhiqiang
2019-07-05 9:56 ` [PATCHv6 28/28] PCI: mobiveil: Fix the potential INTx missing problem Hou Zhiqiang
2019-07-08 11:35 ` [PATCHv6 00/28] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Lorenzo Pieralisi
2019-07-10 10:59 ` Z.q. Hou
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