From: Vivek Gautam <vivek.gautam@codeaurora.org>
To: agross@kernel.org, robh+dt@kernel.org, bjorn.andersson@linaro.org
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>,
Vivek Gautam <vivek.gautam@codeaurora.org>
Subject: [PATCH 1/1] arm64: dts: sdm845: Add device node for Last level cache controller
Date: Wed, 10 Jul 2019 16:59:24 +0530 [thread overview]
Message-ID: <20190710112924.17724-1-vivek.gautam@codeaurora.org> (raw)
From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Last level cache (aka. system cache) controller provides control
over the last level cache present on SDM845. This cache lies after
the memory noc, right before the DDR.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 4babff5f19b5..314241a99290 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1275,6 +1275,13 @@
};
};
+ cache-controller@1100000 {
+ compatible = "qcom,sdm845-llcc";
+ reg = <0 0x1100000 0 0x200000>, <0 0x1300000 0 0x50000>;
+ reg-names = "llcc_base", "llcc_broadcast_base";
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
next reply other threads:[~2019-07-10 11:29 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-10 11:29 Vivek Gautam [this message]
2019-08-05 6:35 ` [PATCH 1/1] arm64: dts: sdm845: Add device node for Last level cache controller Vivek Gautam
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