From: Arnd Bergmann <arnd@arndb.de>
To: "Alex Deucher" <alexander.deucher@amd.com>,
"Christian König" <christian.koenig@amd.com>,
"David (ChunMing) Zhou" <David1.Zhou@amd.com>,
"David Airlie" <airlied@linux.ie>,
"Daniel Vetter" <daniel@ffwll.ch>
Cc: Arnd Bergmann <arnd@arndb.de>, Huang Rui <ray.huang@amd.com>,
Evan Quan <evan.quan@amd.com>, xinhui pan <xinhui.pan@amd.com>,
Rex Zhu <Rex.Zhu@amd.com>, Oak Zeng <Oak.Zeng@amd.com>,
Philip Yang <Philip.Yang@amd.com>,
amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
linux-kernel@vger.kernel.org, clang-built-linux@googlegroups.com
Subject: [PATCH] drm/amd: work around llvm bug #42576
Date: Fri, 12 Jul 2019 11:34:57 +0200 [thread overview]
Message-ID: <20190712093508.1420279-1-arnd@arndb.de> (raw)
Code in the amdgpu driver triggers a bug when using clang to build
an arm64 kernel:
/tmp/sdma_v4_0-f95fd3.s: Assembler messages:
/tmp/sdma_v4_0-f95fd3.s:44: Error: selected processor does not support `bfc w0,#1,#5'
I expect this to be fixed in llvm soon, but we can also work around
it by inserting a barrier() that prevents the optimization.
Link: https://bugs.llvm.org/show_bug.cgi?id=42576
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
Sending this for completeness, please decide for yourselves whether to
apply it or not, given that it's a trivial workaround but probably not
needed in the long run.
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 4428018672d3..154416a626df 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -773,6 +773,7 @@ static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
/* Set ring buffer size in dwords */
uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
+ barrier(); /* work around https://bugs.llvm.org/show_bug.cgi?id=42576 */
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
#ifdef __BIG_ENDIAN
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
--
2.20.0
reply other threads:[~2019-07-12 9:35 UTC|newest]
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