[v1,33/50] ARM: dts: exynos: set parent clocks to UARTs in Exynos5420
diff mbox series

Message ID 20190715124417.4787-34-l.luba@partner.samsung.com
State New
Headers show
Series
  • Exynos5x clocks and buses changes
Related show

Commit Message

Lukasz Luba July 15, 2019, 12:44 p.m. UTC 
Change the parents of UART clocks to the CPLL which has 666MHz.
The UARTs' dividers use /10 rate so they would have 66.6MHz.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Krzysztof Kozlowski July 17, 2019, 10:35 a.m. UTC | #1 
On Mon, 15 Jul 2019 at 14:45, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> Change the parents of UART clocks to the CPLL which has 666MHz.
> The UARTs' dividers use /10 rate so they would have 66.6MHz.

Write also the state before to show what is being fixed (I assume
previous frequency was not best choice).

BR,
Krzysztof

Patch
diff mbox series 

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 18c5273091bd..79f635043247 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1486,6 +1486,8 @@ 
 &serial_0 {
 	clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 	clock-names = "uart", "clk_uart_baud0";
+	assigned-clocks = <&clock CLK_MOUT_UART0>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_CPLL>;
 	dmas = <&pdma0 13>, <&pdma0 14>;
 	dma-names = "rx", "tx";
 };
@@ -1493,6 +1495,8 @@ 
 &serial_1 {
 	clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 	clock-names = "uart", "clk_uart_baud0";
+	assigned-clocks = <&clock CLK_MOUT_UART1>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_CPLL>;
 	dmas = <&pdma1 15>, <&pdma1 16>;
 	dma-names = "rx", "tx";
 };
@@ -1500,6 +1504,8 @@ 
 &serial_2 {
 	clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 	clock-names = "uart", "clk_uart_baud0";
+	assigned-clocks = <&clock CLK_MOUT_UART2>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_CPLL>;
 	dmas = <&pdma0 15>, <&pdma0 16>;
 	dma-names = "rx", "tx";
 };
@@ -1507,6 +1513,8 @@ 
 &serial_3 {
 	clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 	clock-names = "uart", "clk_uart_baud0";
+	assigned-clocks = <&clock CLK_MOUT_UART3>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_CPLL>;
 	dmas = <&pdma1 17>, <&pdma1 18>;
 	dma-names = "rx", "tx";
 };