[v1,26/50] ARM: dts: exynos: align NOC100 bus OPPs in Exynos5420
diff mbox series

Message ID 20190715124417.4787-27-l.luba@partner.samsung.com
State New, archived
Headers show
Series
  • Exynos5x clocks and buses changes
Related show

Commit Message

Lukasz Luba July 15, 2019, 12:43 p.m. UTC
The NOC100 has a parent which clock rate is set tot 400MHz. The OPPs which
are not possible to set are removed and new one is added.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

Comments

Krzysztof Kozlowski July 17, 2019, 10:10 a.m. UTC | #1
On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> The NOC100 has a parent which clock rate is set tot 400MHz. The OPPs which
> are not possible to set are removed and new one is added.

I think it is just NOC bus... or are there more of such and this is 100 MHz one?

Best regards,
Krzysztof
Lukasz Luba July 17, 2019, 10:27 a.m. UTC | #2
On 7/17/19 12:10 PM, Krzysztof Kozlowski wrote:
> On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>>
>> The NOC100 has a parent which clock rate is set tot 400MHz. The OPPs which
>> are not possible to set are removed and new one is added.
> 
> I think it is just NOC bus... or are there more of such and this is 100 MHz one?
Yes, there is a bus NOC100 with a dedicated clock tree in the HW (with
3 muxes and one divider), which makes possible to take different PLL as
a source then WCORE have, divide the rate from it and even switch for a
while to alternative stable PLL (on the 2nd mux to SPLL (after a
divider)) to wait for main PLL rate change stability delay. Max rate is
limited to 100MHz for this NOC100 bus.

Regards,
Lukasz
> 
> Best regards,
> Krzysztof
> 
>
Krzysztof Kozlowski July 17, 2019, 10:38 a.m. UTC | #3
On Wed, 17 Jul 2019 at 12:27, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
>
> On 7/17/19 12:10 PM, Krzysztof Kozlowski wrote:
> > On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
> >>
> >> The NOC100 has a parent which clock rate is set tot 400MHz. The OPPs which
> >> are not possible to set are removed and new one is added.
> >
> > I think it is just NOC bus... or are there more of such and this is 100 MHz one?
> Yes, there is a bus NOC100 with a dedicated clock tree in the HW (with
> 3 muxes and one divider), which makes possible to take different PLL as
> a source then WCORE have, divide the rate from it and even switch for a
> while to alternative stable PLL (on the 2nd mux to SPLL (after a
> divider)) to wait for main PLL rate change stability delay. Max rate is
> limited to 100MHz for this NOC100 bus.

I think we misunderstood each other. I am saying, that the bus is
called "NOC" in the DTSI. Not NOC100. So unless there are more of
NOCs, stick to existing name NOC, even if it is not the most accurate.

Best regards,
Krzysztof
Lukasz Luba July 17, 2019, 10:41 a.m. UTC | #4
On 7/17/19 12:38 PM, Krzysztof Kozlowski wrote:
> On Wed, 17 Jul 2019 at 12:27, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>>
>>
>> On 7/17/19 12:10 PM, Krzysztof Kozlowski wrote:
>>> On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>>>>
>>>> The NOC100 has a parent which clock rate is set tot 400MHz. The OPPs which
>>>> are not possible to set are removed and new one is added.
>>>
>>> I think it is just NOC bus... or are there more of such and this is 100 MHz one?
>> Yes, there is a bus NOC100 with a dedicated clock tree in the HW (with
>> 3 muxes and one divider), which makes possible to take different PLL as
>> a source then WCORE have, divide the rate from it and even switch for a
>> while to alternative stable PLL (on the 2nd mux to SPLL (after a
>> divider)) to wait for main PLL rate change stability delay. Max rate is
>> limited to 100MHz for this NOC100 bus.
> 
> I think we misunderstood each other. I am saying, that the bus is
> called "NOC" in the DTSI. Not NOC100. So unless there are more of
> NOCs, stick to existing name NOC, even if it is not the most accurate.
OK, got it, thanks!

Lukasz
> 
> Best regards,
> Krzysztof
> 
>

Patch
diff mbox series

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 1097fa758d9e..f8c36ff0d4c3 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1135,12 +1135,9 @@ 
 				opp-hz = /bits/ 64 <67000000>;
 			};
 			opp01 {
-				opp-hz = /bits/ 64 <75000000>;
+				opp-hz = /bits/ 64 <80000000>;
 			};
 			opp02 {
-				opp-hz = /bits/ 64 <86000000>;
-			};
-			opp03 {
 				opp-hz = /bits/ 64 <100000000>;
 			};
 		};