From: Andrey Smirnov <andrew.smirnov@gmail.com>
To: linux-crypto@vger.kernel.org
Cc: "Andrey Smirnov" <andrew.smirnov@gmail.com>,
"Chris Spencer" <christopher.spencer@sea.co.uk>,
"Cory Tusar" <cory.tusar@zii.aero>,
"Chris Healy" <cphealy@gmail.com>,
"Lucas Stach" <l.stach@pengutronix.de>,
"Horia Geantă" <horia.geanta@nxp.com>,
"Aymen Sghaier" <aymen.sghaier@nxp.com>,
"Leonard Crestez" <leonard.crestez@nxp.com>,
linux-kernel@vger.kernel.org
Subject: [PATCH v5 13/14] crypto: caam - always select job ring via RSR on i.MX8MQ
Date: Mon, 15 Jul 2019 13:19:41 -0700 [thread overview]
Message-ID: <20190715201942.17309-14-andrew.smirnov@gmail.com> (raw)
In-Reply-To: <20190715201942.17309-1-andrew.smirnov@gmail.com>
Per feedback from NXP tech support the way to use register based
service interface on i.MX8MQ is to follow the same set of steps
outlined for the case when virtualization is enabled, regardless if it
is. Current version of SRM for i.MX8MQ speaks of DECO DID_MS and DECO
DID_LS registers, but apparently those are not implemented, so the
case when SCFGR[VIRT_EN]=0 should be handles the same as the case when
SCFGR[VIRT_EN]=1
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Chris Spencer <christopher.spencer@sea.co.uk>
Cc: Cory Tusar <cory.tusar@zii.aero>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Horia Geantă <horia.geanta@nxp.com>
Cc: Aymen Sghaier <aymen.sghaier@nxp.com>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: linux-crypto@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
drivers/crypto/caam/ctrl.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index b309535f3157..ad6ff4040bab 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -97,7 +97,12 @@ static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
int i;
- if (ctrlpriv->virt_en == 1) {
+ if (ctrlpriv->virt_en == 1 ||
+ /*
+ * Apparently on i.MX8MQ it doesn't matter if virt_en == 1
+ * and the following steps should be performed regardless
+ */
+ of_machine_is_compatible("fsl,imx8mq")) {
clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);
while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
--
2.21.0
next prev parent reply other threads:[~2019-07-15 20:20 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-15 20:19 [PATCH v5 00/14] crypto: caam - Add i.MX8MQ support Andrey Smirnov
2019-07-15 20:19 ` [PATCH v5 01/14] crypto: caam - move DMA mask selection into a function Andrey Smirnov
2019-07-15 20:19 ` [PATCH v5 02/14] crypto: caam - simplfy clock initialization Andrey Smirnov
2019-07-17 7:08 ` Iuliana Prodan
2019-07-15 20:19 ` [PATCH v5 03/14] crypto: caam - convert caam_jr_init() to use devres Andrey Smirnov
2019-07-15 20:19 ` [PATCH v5 04/14] crypto: caam - request JR IRQ as the last step Andrey Smirnov
2019-07-15 20:19 ` [PATCH v5 05/14] crytpo: caam - make use of iowrite64*_hi_lo in wr_reg64 Andrey Smirnov
2019-07-15 20:19 ` [PATCH v5 06/14] crypto: caam - use ioread64*_hi_lo in rd_reg64 Andrey Smirnov
2019-07-15 20:19 ` [PATCH v5 07/14] crypto: caam - drop 64-bit only wr/rd_reg64() Andrey Smirnov
2019-07-15 20:19 ` [PATCH v5 08/14] crypto: caam - make CAAM_PTR_SZ dynamic Andrey Smirnov
2019-07-15 20:19 ` [PATCH v5 09/14] crypto: caam - move cpu_to_caam_dma() selection to runtime Andrey Smirnov
2019-07-15 20:19 ` [PATCH v5 10/14] crypto: caam - drop explicit usage of struct jr_outentry Andrey Smirnov
2019-07-15 20:19 ` [PATCH v5 11/14] crypto: caam - don't hardcode inpentry size Andrey Smirnov
2019-07-16 1:45 ` Andrey Smirnov
2019-07-15 20:19 ` [PATCH v5 12/14] crypto: caam - force DMA address to 32-bit on 64-bit i.MX SoCs Andrey Smirnov
2019-07-15 20:19 ` Andrey Smirnov [this message]
2019-07-15 20:19 ` [PATCH v5 14/14] crypto: caam - add clock entry for i.MX8MQ Andrey Smirnov
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