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From: <Tudor.Ambarus@microchip.com>
To: <vigneshr@ti.com>, <marek.vasut@gmail.com>
Cc: <dwmw2@infradead.org>, <computersforpeace@gmail.com>,
	<miquel.raynal@bootlin.com>, <richard@nod.at>,
	<boris.brezillon@collabora.com>, <linux-mtd@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <Nicolas.Ferre@microchip.com>,
	<Tudor.Ambarus@microchip.com>
Subject: [PATCH 2/5] mtd: spi-nor: group the code about the write protection at power-up
Date: Wed, 17 Jul 2019 08:48:09 +0000	[thread overview]
Message-ID: <20190717084745.19322-3-tudor.ambarus@microchip.com> (raw)
In-Reply-To: <20190717084745.19322-1-tudor.ambarus@microchip.com>

From: Tudor Ambarus <tudor.ambarus@microchip.com>

The write protection at power-up logic was split across functions
because of a dependency to spansion_quad_enable(). Group the code
in spi_nor_init() as the pointer to spansion_quad_enable() can be
retrieved from nor->quad_enable.

While touching this code, rename nor->clear_sr_bp() to
nor->disable_write_protection() to better indicate its scope: it
disables the default write protection after a power-on reset cycle.

No functional change intended.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
 drivers/mtd/spi-nor/spi-nor.c | 39 ++++++++++++++++++++++++---------------
 include/linux/mtd/spi-nor.h   |  6 +++---
 2 files changed, 27 insertions(+), 18 deletions(-)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 03cc788511d5..e9e441f91b68 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -3780,8 +3780,6 @@ static int spi_nor_init_params(struct spi_nor *nor,
 		default:
 			/* Kept only for backward compatibility purpose. */
 			params->quad_enable = spansion_quad_enable;
-			if (nor->clear_sr_bp)
-				nor->clear_sr_bp = spi_nor_spansion_clear_sr_bp;
 			break;
 		}
 
@@ -4034,11 +4032,32 @@ static int spi_nor_init(struct spi_nor *nor)
 {
 	int err;
 
-	if (nor->clear_sr_bp) {
-		err = nor->clear_sr_bp(nor);
+	/*
+	 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
+	 * with the software protection bits set.
+	 */
+	if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
+	    JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
+	    JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
+	    nor->info->flags & SPI_NOR_HAS_LOCK) {
+		nor->disable_write_protection = spi_nor_clear_sr_bp;
+
+		/*
+		 * In case of spansion flashes, when the configuration register
+		 * Quad Enable bit is one, only the the Write Status (01h)
+		 * command with two data bytes may be used to clear the block
+		 * protection bits.
+		 */
+		if (nor->quad_enable == spansion_quad_enable)
+			nor->disable_write_protection =
+				spi_nor_spansion_clear_sr_bp;
+	}
+
+	if (nor->disable_write_protection) {
+		err = nor->disable_write_protection(nor);
 		if (err) {
 			dev_err(nor->dev,
-				"fail to clear block protection bits\n");
+				"failed to unlock the flash at init\n");
 			return err;
 		}
 	}
@@ -4165,16 +4184,6 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
 	if (info->flags & SPI_S3AN)
 		nor->flags |=  SNOR_F_READY_XSR_RDY;
 
-	/*
-	 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
-	 * with the software protection bits set.
-	 */
-	if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
-	    JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
-	    JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
-	    nor->info->flags & SPI_NOR_HAS_LOCK)
-		nor->clear_sr_bp = spi_nor_clear_sr_bp;
-
 	/* Parse the Serial Flash Discoverable Parameters table. */
 	ret = spi_nor_init_params(nor, &params);
 	if (ret)
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index c4c2c5971284..6c3273760700 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -374,8 +374,8 @@ struct flash_info;
  * @flash_is_locked:	[FLASH-SPECIFIC] check if a region of the SPI NOR is
  *			completely locked
  * @quad_enable:	[FLASH-SPECIFIC] enables SPI NOR quad mode
- * @clear_sr_bp:	[FLASH-SPECIFIC] clears the Block Protection Bits from
- *			the SPI NOR Status Register.
+ * @disable_write_protection: [FLASH-SPECIFIC] disable write protection during
+ *                            power-up
  * @priv:		the private data
  */
 struct spi_nor {
@@ -412,7 +412,7 @@ struct spi_nor {
 	int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
 	int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
 	int (*quad_enable)(struct spi_nor *nor);
-	int (*clear_sr_bp)(struct spi_nor *nor);
+	int (*disable_write_protection)(struct spi_nor *nor);
 
 	void *priv;
 };
-- 
2.9.5


  parent reply	other threads:[~2019-07-17  8:48 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-17  8:47 [PATCH 0/5] mtd: spi-nor: write protection at power-up Tudor.Ambarus
2019-07-17  8:48 ` [PATCH 1/5] mtd: spi-nor: fix description for int (*flash_is_locked)() Tudor.Ambarus
2019-08-05  5:34   ` Vignesh Raghavendra
2019-08-12 11:24     ` Tudor.Ambarus
2019-07-17  8:48 ` Tudor.Ambarus [this message]
2019-08-05  5:44   ` [PATCH 2/5] mtd: spi-nor: group the code about the write protection at power-up Vignesh Raghavendra
2019-08-05  6:30     ` Tudor.Ambarus
2019-07-17  8:48 ` [PATCH 3/5] mtd: spi-nor: add Global Block Unlock support Tudor.Ambarus
2019-08-05  6:18   ` Vignesh Raghavendra
2019-07-17  8:48 ` [PATCH 4/5] mtd: spi-nor: unlock global block protection on sst26vf064b Tudor.Ambarus
2019-07-17  8:48 ` [PATCH 5/5] mtd: spi-nor: add Kconfig option to disable write protection at power-up Tudor.Ambarus
2019-07-17 11:15   ` Tudor.Ambarus
2019-07-17 11:30     ` [PATCH v2 " Tudor.Ambarus
2019-08-07 16:24       ` Vignesh Raghavendra

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