[v2,3/4] media: Fix Lane mapping in Cadence CSI2TX
diff mbox series

Message ID 20190722082223.18693-4-jank@cadence.com
State In Next
Commit 6ded416d4ac4ecbf104b897661cdfa2cdacf022a
Headers show
Series
  • media: Add support for Cadence CSI2TX version 2.1
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Commit Message

Jan Kotas July 22, 2019, 8:22 a.m. UTC
This patch fixes mapping of lanes in DPHY_CFG register
of the controller. In the register, bit 0 means first data lane.
In Linux we currently assume lane 0 is clock.

Signed-off-by: Jan Kotas <jank@cadence.com>
---
 drivers/media/platform/cadence/cdns-csi2tx.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Patch
diff mbox series

diff --git a/drivers/media/platform/cadence/cdns-csi2tx.c b/drivers/media/platform/cadence/cdns-csi2tx.c
index 232259c71..c72c8a065 100644
--- a/drivers/media/platform/cadence/cdns-csi2tx.c
+++ b/drivers/media/platform/cadence/cdns-csi2tx.c
@@ -236,7 +236,7 @@  static int csi2tx_start(struct csi2tx_priv *csi2tx)
 	/* Put our lanes (clock and data) out of reset */
 	reg = CSI2TX_DPHY_CFG_CLK_RESET | CSI2TX_DPHY_CFG_MODE_LPDT;
 	for (i = 0; i < csi2tx->num_lanes; i++)
-		reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i]);
+		reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i] - 1);
 	writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG);
 
 	udelay(10);
@@ -244,7 +244,7 @@  static int csi2tx_start(struct csi2tx_priv *csi2tx)
 	/* Enable our (clock and data) lanes */
 	reg |= CSI2TX_DPHY_CFG_CLK_ENABLE;
 	for (i = 0; i < csi2tx->num_lanes; i++)
-		reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i]);
+		reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i] - 1);
 	writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG);
 
 	udelay(10);