[RFC/RFT,1/5] phy: exynos5-usbdrd: read from correct offset of xhci linksystem
diff mbox series

Message ID 20190722185938.9043-2-linux.amoon@gmail.com
State New
Headers show
Series
  • Exynos USB 3.0 PHY tune setting
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Commit Message

Anand Moon July 22, 2019, 6:59 p.m. UTC
Read from linksystem offset to update the xhci version.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 drivers/phy/samsung/phy-exynos5-usbdrd.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Krzysztof Kozlowski July 24, 2019, 10:59 a.m. UTC | #1
On Mon, 22 Jul 2019 at 20:59, Anand Moon <linux.amoon@gmail.com> wrote:
>
> Read from linksystem offset to update the xhci version.

But why? As many times before, you do not specify why you are doing
things. What problem are you solving? What feature are you adding?

Best regards,
Krzysztof

>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
>  drivers/phy/samsung/phy-exynos5-usbdrd.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> index 646259bee909..3c14bf7718c1 100644
> --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
> +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> @@ -397,7 +397,8 @@ static int exynos5_usbdrd_phy_init(struct phy *phy)
>          * Setting the Frame length Adj value[6:1] to default 0x20
>          * See xHCI 1.0 spec, 5.2.4
>          */
> -       reg =   LINKSYSTEM_XHCI_VERSION_CONTROL |
> +       reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM);
> +       reg |=  LINKSYSTEM_XHCI_VERSION_CONTROL |
>                 LINKSYSTEM_FLADJ(0x20);
>         writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM);
>
> --
> 2.22.0
>

Patch
diff mbox series

diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
index 646259bee909..3c14bf7718c1 100644
--- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
+++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
@@ -397,7 +397,8 @@  static int exynos5_usbdrd_phy_init(struct phy *phy)
 	 * Setting the Frame length Adj value[6:1] to default 0x20
 	 * See xHCI 1.0 spec, 5.2.4
 	 */
-	reg =	LINKSYSTEM_XHCI_VERSION_CONTROL |
+	reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM);
+	reg |=	LINKSYSTEM_XHCI_VERSION_CONTROL |
 		LINKSYSTEM_FLADJ(0x20);
 	writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM);