[v2,2/2] dt-bindings: lantiq: Update for new SoC
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Message ID fa6b20015dc6bfe247e1b2a07bdc5c727595a04b.1566288689.git.rahul.tanwar@linux.intel.com
State Superseded
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Series
  • dt-bindings: serial: lantiq: Convert to YAML & add support for new SoC
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Commit Message

Rahul Tanwar Aug. 20, 2019, 8:29 a.m. UTC
Intel Lightning Mountain(LGM) SoC reuses Lantiq ASC serial controller IP.
Update the dt bindings to support LGM as well.

Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
---
 .../devicetree/bindings/serial/lantiq_asc.yaml          | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

Comments

Rob Herring Aug. 20, 2019, 4 p.m. UTC | #1
On Tue, Aug 20, 2019 at 3:29 AM Rahul Tanwar
<rahul.tanwar@linux.intel.com> wrote:
>
> Intel Lightning Mountain(LGM) SoC reuses Lantiq ASC serial controller IP.
> Update the dt bindings to support LGM as well.
>
> Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
> ---
>  .../devicetree/bindings/serial/lantiq_asc.yaml          | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/serial/lantiq_asc.yaml b/Documentation/devicetree/bindings/serial/lantiq_asc.yaml
> index 54b90490f4fb..92807b59b024 100644
> --- a/Documentation/devicetree/bindings/serial/lantiq_asc.yaml
> +++ b/Documentation/devicetree/bindings/serial/lantiq_asc.yaml
> @@ -17,6 +17,7 @@ properties:
>      oneOf:
>        items:
>          - const: lantiq,asc
> +        - const: intel,lgm-asc

Better expressed as:

compatible:
  enum:
    - intel,lgm-asc
    - lantiq,asc

>
>    reg:
>      maxItems: 1
> @@ -28,6 +29,12 @@ properties:
>        - description: tx or combined interrupt
>        - description: rx interrupt
>        - description: err interrupt
> +    description:
> +      For lantiq,asc compatible, it supports 3 separate
> +      interrupts for tx rx & err. Whereas, for intel,lgm-asc
> +      compatible, it supports combined single interrupt for
> +      all of tx, rx & err interrupts.

This can be expressed with an if/then schema. There's some examples in
the tree how to do that.

> +
>
>    clocks:
>      description:
> @@ -67,4 +74,14 @@ examples:
>              interrupts = <112 113 114>;
>      };
>
> +  - |
> +    asc0: serial@e0a00000 {
> +            compatible = "intel,lgm-asc";
> +            reg = <0xe0a00000 0x1000>;
> +            interrupt-parent = <&ioapic1>;
> +            interrupts = <128 1>;
> +            clocks = <&cgu0 LGM_CLK_NOC4>, <&cgu0 LGM_GCLK_ASC0>;
> +            clock-names = "freq", "asc";
> +    };
> +
>  ...
> --
> 2.11.0
>

Patch
diff mbox series

diff --git a/Documentation/devicetree/bindings/serial/lantiq_asc.yaml b/Documentation/devicetree/bindings/serial/lantiq_asc.yaml
index 54b90490f4fb..92807b59b024 100644
--- a/Documentation/devicetree/bindings/serial/lantiq_asc.yaml
+++ b/Documentation/devicetree/bindings/serial/lantiq_asc.yaml
@@ -17,6 +17,7 @@  properties:
     oneOf:
       items:
         - const: lantiq,asc
+        - const: intel,lgm-asc
 
   reg:
     maxItems: 1
@@ -28,6 +29,12 @@  properties:
       - description: tx or combined interrupt
       - description: rx interrupt
       - description: err interrupt
+    description:
+      For lantiq,asc compatible, it supports 3 separate
+      interrupts for tx rx & err. Whereas, for intel,lgm-asc
+      compatible, it supports combined single interrupt for
+      all of tx, rx & err interrupts.
+
 
   clocks:
     description:
@@ -67,4 +74,14 @@  examples:
             interrupts = <112 113 114>;
     };
 
+  - |
+    asc0: serial@e0a00000 {
+            compatible = "intel,lgm-asc";
+            reg = <0xe0a00000 0x1000>;
+            interrupt-parent = <&ioapic1>;
+            interrupts = <128 1>;
+            clocks = <&cgu0 LGM_CLK_NOC4>, <&cgu0 LGM_GCLK_ASC0>;
+            clock-names = "freq", "asc";
+    };
+
 ...