[1/7] iommu/arm-smmu: Support split pagetables
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Message ID 1566327992-362-2-git-send-email-jcrouse@codeaurora.org
State New
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Series
  • iommu/arm-smmu: Split pagetable support for Adreno GPUs
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Commit Message

Jordan Crouse Aug. 20, 2019, 7:06 p.m. UTC
Support a split pagetable format for SMMU models that support it. If
enabled, mirror the TTBR0 setup for TTBR1 and program the pagetable
address in TTBR1 instead of TTBR0.

For now only allow split pagetables for ARM64 stage 1 IOMMUs with 49 bit
upstream buses. This is the only real-life use case for split pagetables
on arm-smmu-v2 to date and it is the easiest configuration to support
without a bunch of extra logic.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
---

 drivers/iommu/arm-smmu.c | 41 +++++++++++++++++++++++++++++++++++++----
 drivers/iommu/arm-smmu.h |  1 +
 2 files changed, 38 insertions(+), 4 deletions(-)

Patch
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diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 49c734a..39e81ef 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -461,7 +461,17 @@  static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
 			cb->tcr[0] = pgtbl_cfg->arm_v7s_cfg.tcr;
 		} else {
 			cb->tcr[0] = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
-			cb->tcr[0] |= TCR_EPD1;
+
+			/*
+			 * For split pagetables, duplicate the T0 configuration
+			 * for T1. Otherwise, disable walks through TTBR1
+			 */
+			if (smmu_domain->split_pagetables)
+				cb->tcr[0] |= (pgtbl_cfg->arm_lpae_s1_cfg.tcr &
+					0xffff) << 16;
+			else
+				cb->tcr[0] |= TCR_EPD1;
+
 			cb->tcr[1] = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32;
 			cb->tcr[1] |= FIELD_PREP(TCR2_SEP, TCR2_SEP_UPSTREAM);
 			if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64)
@@ -477,9 +487,16 @@  static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
 			cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr;
 			cb->ttbr[1] = 0;
 		} else {
-			cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
+			if (smmu_domain->split_pagetables) {
+				cb->ttbr[0] = 0;
+				cb->ttbr[1] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
+			} else {
+				cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
+				cb->ttbr[1] = 0;
+			}
+
 			cb->ttbr[0] |= FIELD_PREP(TTBRn_ASID, cfg->asid);
-			cb->ttbr[1] = FIELD_PREP(TTBRn_ASID, cfg->asid);
+			cb->ttbr[1] |= FIELD_PREP(TTBRn_ASID, cfg->asid);
 		}
 	} else {
 		cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
@@ -720,6 +737,14 @@  static int arm_smmu_init_domain_context(struct iommu_domain *domain,
 			goto out_unlock;
 	}
 
+	/*
+	 * For now, only support a ias of 48 and SEP_UPSTREAM for split
+	 * pagetables. This doesn't preclude using other sign extension bits but
+	 * since the group of split-pagetable users is very small we don't want
+	 * to add a lot of extra code that won't be useful
+	 */
+	WARN_ON(smmu_domain->split_pagetables && ias != 48);
+
 	pgtbl_cfg = (struct io_pgtable_cfg) {
 		.pgsize_bitmap	= smmu->pgsize_bitmap,
 		.ias		= ias,
@@ -740,7 +765,15 @@  static int arm_smmu_init_domain_context(struct iommu_domain *domain,
 
 	/* Update the domain's page sizes to reflect the page table format */
 	domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
-	domain->geometry.aperture_end = (1UL << ias) - 1;
+
+	if (smmu_domain->split_pagetables) {
+		domain->geometry.aperture_start = ~(1UL << ias);
+		domain->geometry.aperture_end = ~0UL;
+	} else {
+		domain->geometry.aperture_start = 0;
+		domain->geometry.aperture_end = (1UL << ias) - 1;
+	}
+
 	domain->geometry.force_aperture = true;
 
 	/* Initialise the context bank with our page table cfg */
diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h
index 7b0e4d2..91a4eb8 100644
--- a/drivers/iommu/arm-smmu.h
+++ b/drivers/iommu/arm-smmu.h
@@ -316,6 +316,7 @@  struct arm_smmu_domain {
 	struct mutex			init_mutex; /* Protects smmu pointer */
 	spinlock_t			cb_lock; /* Serialises ATS1* ops and TLB syncs */
 	struct iommu_domain		domain;
+	bool				split_pagetables;
 };