From: Sam Shih <sam.shih@mediatek.com>
To: Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Thierry Reding <thierry.reding@gmail.com>
Cc: Ryder Lee <ryder.lee@mediatek.com>,
John Crispin <john@phrozen.org>, <linux-pwm@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>,
Sam Shih <sam.shih@mediatek.com>
Subject: [PATCH v5 04/13] pwm: mediatek: allocate the clks array dynamically
Date: Thu, 22 Aug 2019 14:58:34 +0800 [thread overview]
Message-ID: <1566457123-20791-5-git-send-email-sam.shih@mediatek.com> (raw)
In-Reply-To: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com>
Instead of using fixed size of arrays, allocate the memory for them
based on the information we get from the DT.
Also remove the check for num_pwms, due to dynamically allocate pwm
should not cause array index out of bound.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
---
Changes since v5:
- Follow reviewers's comments
Make the changes of allocate the clks array dynamically as a single patch
Changes since v4:
- Follow reviewers's comments
1. use pc->soc->has_clks to check clocks exist or not.
2. Add error message when probe() unable to get clks
- Fixes bug when SoC is old mips which has no complex clock tree.
if clocks not exist, use the new property from DT to apply period caculation;
otherwise, use clk_get_rate to get clock frequency and apply period caculation.
Change-Id: I42edf07548fd604a5a4f689b45e945809057e3e3
---
drivers/pwm/pwm-mediatek.c | 96 ++++++++++++++++++--------------------
1 file changed, 46 insertions(+), 50 deletions(-)
diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
index 1f18bff4800c..8d1fd8163f15 100644
--- a/drivers/pwm/pwm-mediatek.c
+++ b/drivers/pwm/pwm-mediatek.c
@@ -35,25 +35,6 @@
#define PWM_CLK_DIV_MAX 7
-enum {
- MTK_CLK_MAIN = 0,
- MTK_CLK_TOP,
- MTK_CLK_PWM1,
- MTK_CLK_PWM2,
- MTK_CLK_PWM3,
- MTK_CLK_PWM4,
- MTK_CLK_PWM5,
- MTK_CLK_PWM6,
- MTK_CLK_PWM7,
- MTK_CLK_PWM8,
- MTK_CLK_MAX,
-};
-
-static const char * const mtk_pwm_clk_name[MTK_CLK_MAX] = {
- "main", "top", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7",
- "pwm8"
-};
-
struct mtk_pwm_platform_data {
unsigned int fallback_npwms;
bool pwm45_fixup;
@@ -64,13 +45,17 @@ struct mtk_pwm_platform_data {
* struct mtk_pwm_chip - struct representing PWM chip
* @chip: linux PWM chip representation
* @regs: base address of PWM chip
- * @clks: list of clocks
+ * @clk_top: the top clock generator
+ * @clk_main: the clock used by PWM core
+ * @clk_pwms: the clock used by each PWM channel
* @clk_freq: the fix clock frequency of legacy MIPS SoC
*/
struct mtk_pwm_chip {
struct pwm_chip chip;
void __iomem *regs;
- struct clk *clks[MTK_CLK_MAX];
+ struct clk *clk_top;
+ struct clk *clk_main;
+ struct clk **clk_pwms;
unsigned int clk_freq;
const struct mtk_pwm_platform_data *soc;
};
@@ -92,24 +77,24 @@ static int mtk_pwm_clk_enable(struct pwm_chip *chip, struct pwm_device *pwm)
if (!pc->soc->has_clks)
return 0;
- ret = clk_prepare_enable(pc->clks[MTK_CLK_TOP]);
+ ret = clk_prepare_enable(pc->clk_top);
if (ret < 0)
return ret;
- ret = clk_prepare_enable(pc->clks[MTK_CLK_MAIN]);
+ ret = clk_prepare_enable(pc->clk_main);
if (ret < 0)
goto disable_clk_top;
- ret = clk_prepare_enable(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]);
+ ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]);
if (ret < 0)
goto disable_clk_main;
return 0;
disable_clk_main:
- clk_disable_unprepare(pc->clks[MTK_CLK_MAIN]);
+ clk_disable_unprepare(pc->clk_main);
disable_clk_top:
- clk_disable_unprepare(pc->clks[MTK_CLK_TOP]);
+ clk_disable_unprepare(pc->clk_top);
return ret;
}
@@ -121,9 +106,9 @@ static void mtk_pwm_clk_disable(struct pwm_chip *chip, struct pwm_device *pwm)
if (!pc->soc->has_clks)
return;
- clk_disable_unprepare(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]);
- clk_disable_unprepare(pc->clks[MTK_CLK_MAIN]);
- clk_disable_unprepare(pc->clks[MTK_CLK_TOP]);
+ clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]);
+ clk_disable_unprepare(pc->clk_main);
+ clk_disable_unprepare(pc->clk_top);
}
static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num,
@@ -149,13 +134,10 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
u64 resolution;
int ret;
- if (pc->soc->has_clks) {
- struct clk *clk = pc->clks[MTK_CLK_PWM1 + pwm->hwpwm];
-
- clk_freq = clk_get_rate(clk);
- } else {
+ if (pc->soc->has_clks)
+ clk_freq = clk_get_rate(pc->clk_pwms[pwm->hwpwm]);
+ else
clk_freq = pc->clk_freq;
- }
ret = mtk_pwm_clk_enable(chip, pwm);
if (ret < 0)
@@ -239,7 +221,7 @@ static int mtk_pwm_probe(struct platform_device *pdev)
struct device_node *np = pdev->dev.of_node;
struct mtk_pwm_chip *pc;
struct resource *res;
- unsigned int i, npwms;
+ unsigned int npwms;
int ret;
pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
@@ -265,22 +247,36 @@ static int mtk_pwm_probe(struct platform_device *pdev)
}
}
- /* MAIN + TOP + NPWM < MTK_CLK_MAX */
- if ((npwms + 2) > MTK_CLK_MAX) {
- dev_warn(&pdev->dev, "number of PWMs is larger than %d\n",
- MTK_CLK_MAX - 2);
- npwms = MTK_CLK_MAX - 2;
- }
-
if (pc->soc->has_clks) {
- for (i = 0; i < npwms + 2 ; i++) {
- pc->clks[i] = devm_clk_get(&pdev->dev,
- mtk_pwm_clk_name[i]);
- if (IS_ERR(pc->clks[i])) {
+ int i;
+
+ pc->clk_pwms = devm_kcalloc(&pdev->dev, npwms,
+ sizeof(*pc->clk_pwms), GFP_KERNEL);
+ if (!pc->clk_pwms)
+ return -ENOMEM;
+
+ pc->clk_top = devm_clk_get(&pdev->dev, "top");
+ if (IS_ERR(pc->clk_top)) {
+ dev_err(&pdev->dev, "clock: top fail: %ld\n",
+ PTR_ERR(pc->clk_top));
+ return PTR_ERR(pc->clk_top);
+ }
+
+ pc->clk_main = devm_clk_get(&pdev->dev, "main");
+ if (IS_ERR(pc->clk_main)) {
+ dev_err(&pdev->dev, "clock: main fail: %ld\n",
+ PTR_ERR(pc->clk_main));
+ return PTR_ERR(pc->clk_main);
+ }
+ for (i = 0; i < npwms; i++) {
+ char name[8];
+
+ snprintf(name, sizeof(name), "pwm%d", i + 1);
+ pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
+ if (IS_ERR(pc->clk_pwms[i])) {
dev_err(&pdev->dev, "clock: %s fail: %ld\n",
- mtk_pwm_clk_name[i],
- PTR_ERR(pc->clks[i]));
- return PTR_ERR(pc->clks[i]);
+ name, PTR_ERR(pc->clk_pwms[i]));
+ return PTR_ERR(pc->clk_pwms[i]);
}
}
} else {
--
2.17.1
next prev parent reply other threads:[~2019-08-22 7:01 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-22 6:58 [PATCH v5 0/13] Add mt7629 and fix mt7628 pwm Sam Shih
2019-08-22 6:58 ` [PATCH v5 01/13] pwm: mediatek: add a property "num-pwms" Sam Shih
2019-08-24 0:28 ` Uwe Kleine-König
2019-08-22 6:58 ` [PATCH v5 02/13] pwm: mediatek: droping the check for of_device_get_match_data Sam Shih
2019-08-24 0:29 ` Uwe Kleine-König
2019-08-22 6:58 ` [PATCH v5 03/13] pwm: mediatek: add a property "clock-frequency" Sam Shih
2019-08-24 0:32 ` Uwe Kleine-König
2019-08-22 6:58 ` Sam Shih [this message]
2019-08-24 0:33 ` [PATCH v5 04/13] pwm: mediatek: allocate the clks array dynamically Uwe Kleine-König
2019-08-22 6:58 ` [PATCH v5 05/13] pwm: mediatek: use pwm_mediatek as common prefix Sam Shih
2019-08-24 0:34 ` Uwe Kleine-König
2019-08-22 6:58 ` [PATCH v5 06/13] pwm: mediatek: update license and switch to SPDX tag Sam Shih
2019-08-24 0:35 ` Uwe Kleine-König
2019-08-22 6:58 ` [PATCH v5 07/13] dt-bindings: pwm: add a property "num-pwms" Sam Shih
2019-08-27 18:39 ` Rob Herring
2019-09-02 16:04 ` Uwe Kleine-König
2019-09-05 3:27 ` Sam Shih
2019-09-12 1:33 ` Sam Shih
2019-08-22 6:58 ` [PATCH v5 08/13] dt-bindings: pwm: update bindings for MT7628 SoC Sam Shih
2019-08-22 8:12 ` Yingjoe Chen
2019-08-24 0:36 ` Uwe Kleine-König
2019-08-22 6:58 ` [PATCH v5 09/13] arm64: dts: mt7622: add a property "num-pwms" for PWM Sam Shih
2019-08-24 0:38 ` Uwe Kleine-König
2019-08-22 6:58 ` [PATCH v5 10/13] arm: dts: mt7623: " Sam Shih
2019-08-24 0:38 ` Uwe Kleine-König
2019-08-22 6:58 ` [PATCH v5 11/13] dt-bindings: pwm: update bindings for MT7629 SoC Sam Shih
2019-08-24 0:39 ` Uwe Kleine-König
2019-08-22 6:58 ` [PATCH v5 12/13] pwm: mediatek: remove a property "has-clock" Sam Shih
2019-08-24 0:41 ` Uwe Kleine-König
2019-08-22 6:58 ` [PATCH v5 13/13] arm: dts: mediatek: add mt7629 pwm support Sam Shih
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