From: Dilip Kota <eswara.kota@linux.intel.com>
To: p.zabel@pengutronix.de, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: cheol.yong.kim@intel.com, chuanhua.lei@linux.intel.com,
qi-ming.wu@intel.com, Dilip Kota <eswara.kota@linux.intel.com>
Subject: [PATCH 1/2] dt-bindings: reset: Add YAML schemas for the Intel Reset controller
Date: Thu, 22 Aug 2019 15:32:10 +0800 [thread overview]
Message-ID: <c909a3a19a1c06ac3ed9e1c42da3193ff8e43b7a.1566454535.git.eswara.kota@linux.intel.com> (raw)
Add YAML schemas for the reset controller on Intel
Lightening Mountain (LGM) SoC.
Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com>
---
.../bindings/reset/intel,syscon-reset.yaml | 50 ++++++++++++++++++++++
1 file changed, 50 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
diff --git a/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml b/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
new file mode 100644
index 000000000000..298c60085486
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/intel,syscon-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel Lightening Mountain SoC System Reset Controller
+
+maintainers:
+ - Dilip Kota <eswara.kota@linux.intel.com>
+
+properties:
+ compatible:
+ allOf:
+ - items:
+ - enum:
+ - intel,rcu-lgm
+ - syscon
+
+ reg:
+ description: Reset controller register base address and size
+
+ intel,global-reset:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: Global reset register offset and bit offset.
+
+ "#reset-cells":
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - intel,global-reset
+ - "#reset-cells"
+
+examples:
+ - |
+ rcu0: reset-controller@00000000 {
+ compatible = "intel,rcu-lgm", "syscon";
+ reg = <0x000000 0x80000>;
+ intel,global-reset = <0x10 30>;
+ #reset-cells = <2>;
+ };
+
+ pcie_phy0: pciephy@... {
+ ...
+ /* address offset: 0x10, bit offset: 12 */
+ resets = <&rcu0 0x10 12>;
+ ...
+ };
--
2.11.0
next reply other threads:[~2019-08-22 7:32 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-22 7:32 Dilip Kota [this message]
2019-08-22 7:32 ` [PATCH 2/2] reset: Reset controller driver for Intel LGM SoC Dilip Kota
2019-08-22 17:54 ` [PATCH 1/2] dt-bindings: reset: Add YAML schemas for the Intel Reset controller Rob Herring
2019-08-23 5:22 ` Dilip Kota
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