From: <Tudor.Ambarus@microchip.com>
To: <boris.brezillon@collabora.com>, <marek.vasut@gmail.com>,
<vigneshr@ti.com>, <miquel.raynal@bootlin.com>, <richard@nod.at>,
<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Cc: <Tudor.Ambarus@microchip.com>
Subject: [PATCH v2 7/7] mtd: spi-nor: Rework the disabling of block write protection
Date: Sat, 24 Aug 2019 12:00:48 +0000 [thread overview]
Message-ID: <20190824120027.14452-8-tudor.ambarus@microchip.com> (raw)
In-Reply-To: <20190824120027.14452-1-tudor.ambarus@microchip.com>
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Get rid of MFR handling and implement specific manufacturer
default_init() fixup hooks.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 30 ++++++++++++++++++++----------
1 file changed, 20 insertions(+), 10 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index fc9e14777212..f4e9fcca619f 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -4146,6 +4146,16 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor,
return err;
}
+static void atmel_set_default_init(struct spi_nor *nor)
+{
+ nor->params.disable_block_protection = spi_nor_clear_sr_bp;
+}
+
+static void intel_set_default_init(struct spi_nor *nor)
+{
+ nor->params.disable_block_protection = spi_nor_clear_sr_bp;
+}
+
static void macronix_set_default_init(struct spi_nor *nor)
{
nor->params.quad_enable = macronix_quad_enable;
@@ -4173,6 +4183,14 @@ static void spi_nor_manufacturer_init_params(struct spi_nor *nor)
{
/* Init flash parameters based on MFR */
switch (JEDEC_MFR(nor->info)) {
+ case SNOR_MFR_ATMEL:
+ atmel_set_default_init(nor);
+ break;
+
+ case SNOR_MFR_INTEL:
+ intel_set_default_init(nor);
+ break;
+
case SNOR_MFR_MACRONIX:
macronix_set_default_init(nor);
break;
@@ -4760,18 +4778,10 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
if (info->flags & SPI_S3AN)
nor->flags |= SNOR_F_READY_XSR_RDY;
- if (info->flags & SPI_NOR_HAS_LOCK)
+ if (info->flags & SPI_NOR_HAS_LOCK) {
nor->flags |= SNOR_F_HAS_LOCK;
-
- /*
- * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
- * with the software protection bits set.
- */
- if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
- JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
- JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
- nor->info->flags & SPI_NOR_HAS_LOCK)
nor->params.disable_block_protection = spi_nor_clear_sr_bp;
+ }
/* Init flash parameters based on flash_info struct and SFDP */
spi_nor_init_params(nor);
--
2.9.5
next prev parent reply other threads:[~2019-08-24 12:01 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-24 12:00 [PATCH v2 0/7] mtd: spi-nor: move manuf out of the core - batch 1 Tudor.Ambarus
2019-08-24 12:00 ` [PATCH v2 1/7] mtd: spi-nor: Add default_init() hook to tweak flash parameters Tudor.Ambarus
2019-08-24 12:00 ` [PATCH v2 2/7] mtd: spi-nor: Add a default_init() fixup hook for gd25q256 Tudor.Ambarus
2019-08-24 12:00 ` [PATCH v2 3/7] mtd: spi_nor: Move manufacturer quad_enable() in ->default_init() Tudor.Ambarus
2019-08-25 11:47 ` Boris Brezillon
2019-08-25 13:08 ` Tudor.Ambarus
2019-08-24 12:00 ` [PATCH v2 4/7] mtd: spi-nor: Split spi_nor_init_params() Tudor.Ambarus
2019-08-25 12:03 ` Boris Brezillon
2019-08-25 12:23 ` Tudor.Ambarus
2019-08-25 12:51 ` Boris Brezillon
2019-08-24 12:00 ` [PATCH v2 5/7] mtd: spi-nor: Create a ->set_4byte() method Tudor.Ambarus
2019-08-24 12:00 ` [PATCH v2 6/7] mtd: spi-nor: Rework the SPI NOR lock/unlock logic Tudor.Ambarus
2019-08-25 12:26 ` Boris Brezillon
2019-08-25 13:10 ` Tudor.Ambarus
2019-08-24 12:00 ` Tudor.Ambarus [this message]
2019-08-25 12:24 ` [PATCH v2 7/7] mtd: spi-nor: Rework the disabling of block write protection Boris Brezillon
2019-08-25 12:57 ` Tudor.Ambarus
2019-08-25 13:22 ` Boris Brezillon
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