From: Christoph Hellwig <hch@lst.de>
To: Palmer Dabbelt <palmer@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>
Cc: Damien Le Moal <damien.lemoal@wdc.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Marc Zyngier <maz@kernel.org>
Subject: [PATCH 01/20] irqchip/sifive-plic: set max threshold for ignored handlers
Date: Tue, 3 Sep 2019 11:32:20 +0200 [thread overview]
Message-ID: <20190903093239.21278-2-hch@lst.de> (raw)
In-Reply-To: <20190903093239.21278-1-hch@lst.de>
When running in M-mode, the S-mode plic handlers are still listed in the
device tree. Ignore them by setting the maximum threshold.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Marc Zyngier <maz@kernel.org>
---
drivers/irqchip/irq-sifive-plic.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index cf755964f2f8..c72c036aea76 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -244,6 +244,7 @@ static int __init plic_init(struct device_node *node,
struct plic_handler *handler;
irq_hw_number_t hwirq;
int cpu, hartid;
+ u32 threshold = 0;
if (of_irq_parse_one(node, i, &parent)) {
pr_err("failed to parse parent for context %d.\n", i);
@@ -266,10 +267,16 @@ static int __init plic_init(struct device_node *node,
continue;
}
+ /*
+ * When running in M-mode we need to ignore the S-mode handler.
+ * Here we assume it always comes later, but that might be a
+ * little fragile.
+ */
handler = per_cpu_ptr(&plic_handlers, cpu);
if (handler->present) {
pr_warn("handler already present for context %d.\n", i);
- continue;
+ threshold = 0xffffffff;
+ goto done;
}
handler->present = true;
@@ -279,8 +286,9 @@ static int __init plic_init(struct device_node *node,
handler->enable_base =
plic_regs + ENABLE_BASE + i * ENABLE_PER_HART;
+done:
/* priority must be > threshold to trigger an interrupt */
- writel(0, handler->hart_base + CONTEXT_THRESHOLD);
+ writel(threshold, handler->hart_base + CONTEXT_THRESHOLD);
for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
plic_toggle(handler, hwirq, 0);
nr_handlers++;
--
2.20.1
next prev parent reply other threads:[~2019-09-03 9:32 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-03 9:32 RISC-V nommu support v4 Christoph Hellwig
2019-09-03 9:32 ` Christoph Hellwig [this message]
2019-09-03 9:32 ` [PATCH 02/20] riscv: refactor the IPI code Christoph Hellwig
2019-09-03 9:32 ` [PATCH 03/20] riscv: cleanup send_ipi_mask Christoph Hellwig
2019-09-03 9:32 ` [PATCH 04/20] riscv: optimize send_ipi_single Christoph Hellwig
2019-09-03 9:32 ` [PATCH 05/20] riscv: cleanup riscv_cpuid_to_hartid_mask Christoph Hellwig
2019-09-03 9:32 ` [PATCH 06/20] riscv: don't use the rdtime(h) pseudo-instructions Christoph Hellwig
2019-09-03 9:32 ` [PATCH 07/20] riscv: move the TLB flush logic out of line Christoph Hellwig
2019-09-03 9:32 ` [PATCH 08/20] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-10-16 2:07 ` Paul Walmsley
2019-10-17 16:20 ` Christoph Hellwig
2019-09-03 9:32 ` [PATCH 09/20] riscv: don't allow selecting SBI based drivers for M-mode Christoph Hellwig
2019-09-03 9:32 ` [PATCH 10/20] riscv: poison SBI calls " Christoph Hellwig
2019-09-03 9:32 ` [PATCH 11/20] riscv: cleanup the default power off implementation Christoph Hellwig
2019-09-03 9:32 ` [PATCH 12/20] riscv: implement remote sfence.i using IPIs Christoph Hellwig
2019-09-03 9:32 ` [PATCH 13/20] riscv: add support for MMIO access to the timer registers Christoph Hellwig
2019-09-03 9:32 ` [PATCH 14/20] riscv: provide native clint access for M-mode Christoph Hellwig
2019-09-03 9:32 ` [PATCH 15/20] riscv: read the hart ID from mhartid on boot Christoph Hellwig
2019-09-03 9:32 ` [PATCH 16/20] riscv: use the correct interrupt levels for M-mode Christoph Hellwig
2019-09-03 9:32 ` [PATCH 17/20] riscv: clear the instruction cache and all registers when booting Christoph Hellwig
2019-09-03 9:32 ` [PATCH 18/20] riscv: add nommu support Christoph Hellwig
2019-09-03 9:32 ` [PATCH 19/20] riscv: provide a flat image loader Christoph Hellwig
2019-09-03 9:32 ` [PATCH 20/20] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig
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