From: Christoph Hellwig <hch@lst.de>
To: Palmer Dabbelt <palmer@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>
Cc: Damien Le Moal <damien.lemoal@wdc.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Atish Patra <atish.patra@wdc.com>
Subject: [PATCH 05/20] riscv: cleanup riscv_cpuid_to_hartid_mask
Date: Tue, 3 Sep 2019 11:32:24 +0200 [thread overview]
Message-ID: <20190903093239.21278-6-hch@lst.de> (raw)
In-Reply-To: <20190903093239.21278-1-hch@lst.de>
Move the initial clearing of the mask from the callers to
riscv_cpuid_to_hartid_mask, and remove the unused !CONFIG_SMP stub.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
---
arch/riscv/include/asm/smp.h | 6 ------
arch/riscv/include/asm/tlbflush.h | 1 -
arch/riscv/kernel/smp.c | 1 +
arch/riscv/mm/cacheflush.c | 1 -
4 files changed, 1 insertion(+), 8 deletions(-)
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index c6ed4d691def..a83451d73a4e 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -61,11 +61,5 @@ static inline unsigned long cpuid_to_hartid_map(int cpu)
return boot_cpu_hartid;
}
-static inline void riscv_cpuid_to_hartid_mask(const struct cpumask *in,
- struct cpumask *out)
-{
- cpumask_set_cpu(cpuid_to_hartid_map(0), out);
-}
-
#endif /* CONFIG_SMP */
#endif /* _ASM_RISCV_SMP_H */
diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h
index 4d9bbe8438bf..df31fe2ed09c 100644
--- a/arch/riscv/include/asm/tlbflush.h
+++ b/arch/riscv/include/asm/tlbflush.h
@@ -47,7 +47,6 @@ static inline void remote_sfence_vma(struct cpumask *cmask, unsigned long start,
{
struct cpumask hmask;
- cpumask_clear(&hmask);
riscv_cpuid_to_hartid_mask(cmask, &hmask);
sbi_remote_sfence_vma(hmask.bits, start, size);
}
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index a3715d621f60..3836760d7aaf 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -56,6 +56,7 @@ void riscv_cpuid_to_hartid_mask(const struct cpumask *in, struct cpumask *out)
{
int cpu;
+ cpumask_clear(out);
for_each_cpu(cpu, in)
cpumask_set_cpu(cpuid_to_hartid_map(cpu), out);
}
diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
index 9ebcff8ba263..3f15938dec89 100644
--- a/arch/riscv/mm/cacheflush.c
+++ b/arch/riscv/mm/cacheflush.c
@@ -47,7 +47,6 @@ void flush_icache_mm(struct mm_struct *mm, bool local)
cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
local |= cpumask_empty(&others);
if (mm != current->active_mm || !local) {
- cpumask_clear(&hmask);
riscv_cpuid_to_hartid_mask(&others, &hmask);
sbi_remote_fence_i(hmask.bits);
} else {
--
2.20.1
next prev parent reply other threads:[~2019-09-03 9:32 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-03 9:32 RISC-V nommu support v4 Christoph Hellwig
2019-09-03 9:32 ` [PATCH 01/20] irqchip/sifive-plic: set max threshold for ignored handlers Christoph Hellwig
2019-09-03 9:32 ` [PATCH 02/20] riscv: refactor the IPI code Christoph Hellwig
2019-09-03 9:32 ` [PATCH 03/20] riscv: cleanup send_ipi_mask Christoph Hellwig
2019-09-03 9:32 ` [PATCH 04/20] riscv: optimize send_ipi_single Christoph Hellwig
2019-09-03 9:32 ` Christoph Hellwig [this message]
2019-09-03 9:32 ` [PATCH 06/20] riscv: don't use the rdtime(h) pseudo-instructions Christoph Hellwig
2019-09-03 9:32 ` [PATCH 07/20] riscv: move the TLB flush logic out of line Christoph Hellwig
2019-09-03 9:32 ` [PATCH 08/20] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-10-16 2:07 ` Paul Walmsley
2019-10-17 16:20 ` Christoph Hellwig
2019-09-03 9:32 ` [PATCH 09/20] riscv: don't allow selecting SBI based drivers for M-mode Christoph Hellwig
2019-09-03 9:32 ` [PATCH 10/20] riscv: poison SBI calls " Christoph Hellwig
2019-09-03 9:32 ` [PATCH 11/20] riscv: cleanup the default power off implementation Christoph Hellwig
2019-09-03 9:32 ` [PATCH 12/20] riscv: implement remote sfence.i using IPIs Christoph Hellwig
2019-09-03 9:32 ` [PATCH 13/20] riscv: add support for MMIO access to the timer registers Christoph Hellwig
2019-09-03 9:32 ` [PATCH 14/20] riscv: provide native clint access for M-mode Christoph Hellwig
2019-09-03 9:32 ` [PATCH 15/20] riscv: read the hart ID from mhartid on boot Christoph Hellwig
2019-09-03 9:32 ` [PATCH 16/20] riscv: use the correct interrupt levels for M-mode Christoph Hellwig
2019-09-03 9:32 ` [PATCH 17/20] riscv: clear the instruction cache and all registers when booting Christoph Hellwig
2019-09-03 9:32 ` [PATCH 18/20] riscv: add nommu support Christoph Hellwig
2019-09-03 9:32 ` [PATCH 19/20] riscv: provide a flat image loader Christoph Hellwig
2019-09-03 9:32 ` [PATCH 20/20] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig
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