clk: sprd: add missing kfree
diff mbox series

Message ID 20190905103009.27166-1-zhang.lyra@gmail.com
State Accepted
Commit 5e75ea9c67433a065b0e8595ad3c91c7c0ca0d2d
Headers show
Series
  • clk: sprd: add missing kfree
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Commit Message

Chunyan Zhang Sept. 5, 2019, 10:30 a.m. UTC
From: Chunyan Zhang <chunyan.zhang@unisoc.com>

The number of config registers for different pll clocks probably are not
same, so we have to use malloc, and should free the memory before return.

Fixes: 3e37b005580b ("clk: sprd: add adjustable pll support")
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Signed-off-by: Chunyan Zhang <zhang.lyra@gmail.com>
---
 drivers/clk/sprd/pll.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Chunyan Zhang Sept. 12, 2019, 5:47 a.m. UTC | #1
gentle ping

On Thu, 5 Sep 2019 at 18:30, Chunyan Zhang <zhang.lyra@gmail.com> wrote:
>
> From: Chunyan Zhang <chunyan.zhang@unisoc.com>
>
> The number of config registers for different pll clocks probably are not
> same, so we have to use malloc, and should free the memory before return.
>
> Fixes: 3e37b005580b ("clk: sprd: add adjustable pll support")
> Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
> Signed-off-by: Chunyan Zhang <zhang.lyra@gmail.com>
> ---
>  drivers/clk/sprd/pll.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/clk/sprd/pll.c b/drivers/clk/sprd/pll.c
> index 36b4402bf09e..640270f51aa5 100644
> --- a/drivers/clk/sprd/pll.c
> +++ b/drivers/clk/sprd/pll.c
> @@ -136,6 +136,7 @@ static unsigned long _sprd_pll_recalc_rate(const struct sprd_pll *pll,
>                                          k2 + refin * nint * CLK_PLL_1M;
>         }
>
> +       kfree(cfg);
>         return rate;
>  }
>
> @@ -222,6 +223,7 @@ static int _sprd_pll_set_rate(const struct sprd_pll *pll,
>         if (!ret)
>                 udelay(pll->udelay);
>
> +       kfree(cfg);
>         return ret;
>  }
>
> --
> 2.20.1
>
Stephen Boyd Sept. 18, 2019, 5:01 a.m. UTC | #2
Quoting Chunyan Zhang (2019-09-05 03:30:09)
> From: Chunyan Zhang <chunyan.zhang@unisoc.com>
> 
> The number of config registers for different pll clocks probably are not
> same, so we have to use malloc, and should free the memory before return.
> 
> Fixes: 3e37b005580b ("clk: sprd: add adjustable pll support")
> Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
> Signed-off-by: Chunyan Zhang <zhang.lyra@gmail.com>
> ---

Applied to clk-next

Patch
diff mbox series

diff --git a/drivers/clk/sprd/pll.c b/drivers/clk/sprd/pll.c
index 36b4402bf09e..640270f51aa5 100644
--- a/drivers/clk/sprd/pll.c
+++ b/drivers/clk/sprd/pll.c
@@ -136,6 +136,7 @@  static unsigned long _sprd_pll_recalc_rate(const struct sprd_pll *pll,
 					 k2 + refin * nint * CLK_PLL_1M;
 	}
 
+	kfree(cfg);
 	return rate;
 }
 
@@ -222,6 +223,7 @@  static int _sprd_pll_set_rate(const struct sprd_pll *pll,
 	if (!ret)
 		udelay(pll->udelay);
 
+	kfree(cfg);
 	return ret;
 }