From: "tip-bot2 for Tony W Wang-oc" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: "Tony W Wang-oc" <TonyWWang-oc@zhaoxin.com>,
Borislav Petkov <bp@suse.de>,
CooperYan@zhaoxin.com, DavidWang@zhaoxin.com,
HerryYang@zhaoxin.com, "H. Peter Anvin" <hpa@zytor.com>,
Ingo Molnar <mingo@redhat.com>,
"linux-edac" <linux-edac@vger.kernel.org>,
QiyuanWang@zhaoxin.com, Thomas Gleixner <tglx@linutronix.de>,
Tony Luck <tony.luck@intel.com>, "x86-ml" <x86@kernel.org>,
Ingo Molnar <mingo@kernel.org>, Borislav Petkov <bp@alien8.de>,
linux-kernel@vger.kernel.org
Subject: [tip: ras/core] x86/mce: Add Zhaoxin CMCI support
Date: Tue, 01 Oct 2019 11:21:39 -0000 [thread overview]
Message-ID: <156992889955.9978.11127376798004332178.tip-bot2@tip-bot2> (raw)
In-Reply-To: <1568787573-1297-4-git-send-email-TonyWWang-oc@zhaoxin.com>
The following commit has been merged into the ras/core branch of tip:
Commit-ID: 5a3d56a034be9e8e87a6cb9ed3f2928184db1417
Gitweb: https://git.kernel.org/tip/5a3d56a034be9e8e87a6cb9ed3f2928184db1417
Author: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
AuthorDate: Wed, 18 Sep 2019 14:19:32 +08:00
Committer: Borislav Petkov <bp@suse.de>
CommitterDate: Tue, 01 Oct 2019 12:33:09 +02:00
x86/mce: Add Zhaoxin CMCI support
All newer Zhaoxin CPUs support CMCI and are compatible with Intel's
Machine-Check Architecture. Add that support for Zhaoxin CPUs.
[ bp: Massage comments and export intel_init_cmci(). ]
Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: CooperYan@zhaoxin.com
Cc: DavidWang@zhaoxin.com
Cc: HerryYang@zhaoxin.com
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: QiyuanWang@zhaoxin.com
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: x86-ml <x86@kernel.org>
Link: https://lkml.kernel.org/r/1568787573-1297-4-git-send-email-TonyWWang-oc@zhaoxin.com
---
arch/x86/kernel/cpu/mce/core.c | 27 +++++++++++++++++++++++++++
arch/x86/kernel/cpu/mce/intel.c | 6 ++++--
arch/x86/kernel/cpu/mce/internal.h | 2 ++
3 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index a780fe0..1e6b8a4 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1777,6 +1777,29 @@ static void mce_centaur_feature_init(struct cpuinfo_x86 *c)
}
}
+static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
+{
+ struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
+
+ /*
+ * These CPUs have MCA bank 8 which reports only one error type called
+ * SVAD (System View Address Decoder). The reporting of that error is
+ * controlled by IA32_MC8.CTL.0.
+ *
+ * If enabled, prefetching on these CPUs will cause SVAD MCE when
+ * virtual machines start and result in a system panic. Always disable
+ * bank 8 SVAD error by default.
+ */
+ if ((c->x86 == 7 && c->x86_model == 0x1b) ||
+ (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
+ if (this_cpu_read(mce_num_banks) > 8)
+ mce_banks[8].ctl = 0;
+ }
+
+ intel_init_cmci();
+ mce_adjust_timer = cmci_intel_adjust_timer;
+}
+
static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
{
switch (c->x86_vendor) {
@@ -1798,6 +1821,10 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
mce_centaur_feature_init(c);
break;
+ case X86_VENDOR_ZHAOXIN:
+ mce_zhaoxin_feature_init(c);
+ break;
+
default:
break;
}
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index 88cd959..fb6e990 100644
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -85,8 +85,10 @@ static int cmci_supported(int *banks)
* initialization is vendor keyed and this
* makes sure none of the backdoors are entered otherwise.
*/
- if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
+ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
+ boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
return 0;
+
if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6)
return 0;
rdmsrl(MSR_IA32_MCG_CAP, cap);
@@ -423,7 +425,7 @@ void cmci_disable_bank(int bank)
raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
}
-static void intel_init_cmci(void)
+void intel_init_cmci(void)
{
int banks;
diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h
index 43031db..a7ee230 100644
--- a/arch/x86/kernel/cpu/mce/internal.h
+++ b/arch/x86/kernel/cpu/mce/internal.h
@@ -45,11 +45,13 @@ unsigned long cmci_intel_adjust_timer(unsigned long interval);
bool mce_intel_cmci_poll(void);
void mce_intel_hcpu_update(unsigned long cpu);
void cmci_disable_bank(int bank);
+void intel_init_cmci(void);
#else
# define cmci_intel_adjust_timer mce_adjust_timer_default
static inline bool mce_intel_cmci_poll(void) { return false; }
static inline void mce_intel_hcpu_update(unsigned long cpu) { }
static inline void cmci_disable_bank(int bank) { }
+static inline void intel_init_cmci(void) { }
#endif
void mce_timer_kick(unsigned long interval);
next prev parent reply other threads:[~2019-10-01 11:21 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-18 6:19 [PATCH v4 0/4] x86/mce: Add supports for Zhaoxin MCA Tony W Wang-oc
2019-09-18 6:19 ` [PATCH v4 1/4] x86/mce: Add Zhaoxin MCE support Tony W Wang-oc
2019-09-18 6:19 ` [PATCH v4 2/4] x86/mce: Make 3 functions non-static Tony W Wang-oc
2019-09-18 6:19 ` [PATCH v4 3/4] x86/mce: Add Zhaoxin CMCI support Tony W Wang-oc
2019-09-18 6:19 ` [PATCH v4 4/4] x86/mce: Add Zhaoxin LMCE support Tony W Wang-oc
2019-10-01 11:21 ` [tip: ras/core] " tip-bot2 for Tony W Wang-oc
2019-10-01 11:21 ` tip-bot2 for Tony W Wang-oc [this message]
2019-09-30 16:25 ` [PATCH v4 2/4] x86/mce: Make 3 functions non-static Borislav Petkov
2019-10-01 11:21 ` [tip: ras/core] x86/mce: Add Zhaoxin MCE support tip-bot2 for Tony W Wang-oc
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