From: kan.liang@linux.intel.com
To: peterz@infradead.org, mingo@kernel.org, linux-kernel@vger.kernel.org
Cc: ak@linux.intel.com, Kan Liang <kan.liang@linux.intel.com>
Subject: [PATCH 6/9] perf/x86/cstate: Update C-state counters for Ice Lake
Date: Tue, 8 Oct 2019 08:50:07 -0700 [thread overview]
Message-ID: <1570549810-25049-7-git-send-email-kan.liang@linux.intel.com> (raw)
In-Reply-To: <1570549810-25049-1-git-send-email-kan.liang@linux.intel.com>
From: Kan Liang <kan.liang@linux.intel.com>
There is no Core C3 C-State counter for Ice Lake.
Package C8/C9/C10 C-State counters are added for Ice Lake.
Introduce a new event list, icl_cstates, for Ice Lake.
Update the comments accordingly.
Fixes: f08c47d1f86c ("perf/x86/intel/cstate: Add Icelake support")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/intel/cstate.c | 36 +++++++++++++++++++++++++-----------
1 file changed, 25 insertions(+), 11 deletions(-)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 21c65e1..4d232ac 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -50,43 +50,44 @@
* MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
- * SKL,KNL,GLM,CNL,KBL,CML
+ * SKL,KNL,GLM,CNL,KBL,CML,ICL
* Scope: Core
* MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
* perf code: 0x03
- * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML
+ * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
+ * ICL
* Scope: Core
* MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
* perf code: 0x00
* Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
- * KBL,CML
+ * KBL,CML,ICL
* Scope: Package (physical package)
* MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
* perf code: 0x01
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
- * GLM,CNL,KBL,CML
+ * GLM,CNL,KBL,CML,ICL
* Scope: Package (physical package)
* MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter.
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- * SKL,KNL,GLM,CNL,KBL,CML
+ * SKL,KNL,GLM,CNL,KBL,CML,ICL
* Scope: Package (physical package)
* MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
* perf code: 0x03
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL,
- * KBL,CML
+ * KBL,CML,ICL
* Scope: Package (physical package)
* MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter.
* perf code: 0x04
- * Available model: HSW ULT,KBL,CNL,CML
+ * Available model: HSW ULT,KBL,CNL,CML,ICL
* Scope: Package (physical package)
* MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter.
* perf code: 0x05
- * Available model: HSW ULT,KBL,CNL,CML
+ * Available model: HSW ULT,KBL,CNL,CML,ICL
* Scope: Package (physical package)
* MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
* perf code: 0x06
- * Available model: HSW ULT,KBL,GLM,CNL,CML
+ * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL
* Scope: Package (physical package)
*
*/
@@ -546,6 +547,19 @@ static const struct cstate_model cnl_cstates __initconst = {
BIT(PERF_CSTATE_PKG_C10_RES),
};
+static const struct cstate_model icl_cstates __initconst = {
+ .core_events = BIT(PERF_CSTATE_CORE_C6_RES) |
+ BIT(PERF_CSTATE_CORE_C7_RES),
+
+ .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) |
+ BIT(PERF_CSTATE_PKG_C3_RES) |
+ BIT(PERF_CSTATE_PKG_C6_RES) |
+ BIT(PERF_CSTATE_PKG_C7_RES) |
+ BIT(PERF_CSTATE_PKG_C8_RES) |
+ BIT(PERF_CSTATE_PKG_C9_RES) |
+ BIT(PERF_CSTATE_PKG_C10_RES),
+};
+
static const struct cstate_model slm_cstates __initconst = {
.core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
BIT(PERF_CSTATE_CORE_C6_RES),
@@ -629,8 +643,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_PLUS, glm_cstates),
- X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_L, snb_cstates),
- X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE, snb_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_L, icl_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE, icl_cstates),
{ },
};
MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
--
2.7.4
next prev parent reply other threads:[~2019-10-08 15:52 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-08 15:50 [PATCH 0/9] perf: Several update for Comet Lake, Ice Lake and Tiger Lake kan.liang
2019-10-08 15:50 ` [PATCH 1/9] x86/cpu: Add Comet Lake to Intel family kan.liang
2019-10-08 17:05 ` [tip: x86/urgent] x86/cpu: Add Comet Lake to the Intel CPU models header tip-bot2 for Kan Liang
2019-10-08 17:05 ` tip-bot2 for Kan Liang
2019-10-08 15:50 ` [PATCH 2/9] perf/x86/intel: Add Comet Lake CPU support kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
2019-10-08 15:50 ` [PATCH 3/9] perf/x86/msr: " kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
2019-10-08 15:50 ` [PATCH 4/9] perf/x86/cstate: " kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
2019-10-08 15:50 ` [PATCH 5/9] perf/x86/msr: Add more CPU model number for Ice Lake kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] perf/x86/msr: Add new CPU model numbers " tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
2019-10-08 15:50 ` kan.liang [this message]
2019-10-09 12:59 ` [tip: perf/urgent] perf/x86/cstate: Update C-state counters " tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
2019-10-08 15:50 ` [PATCH 7/9] perf/x86/intel: Add Tiger Lake CPU support kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
2019-10-08 15:50 ` [PATCH 8/9] perf/x86/msr: " kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
2019-10-08 15:50 ` [PATCH 9/9] perf/x86/cstate: " kan.liang
2019-10-09 12:59 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
2019-10-12 13:19 ` tip-bot2 for Kan Liang
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