[5/9] perf/x86/msr: Add more CPU model number for Ice Lake
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Message ID 1570549810-25049-6-git-send-email-kan.liang@linux.intel.com
State Accepted
Commit 1a5da78d00ce0152994946debd1417513dc35eb3
Headers show
Series
  • perf: Several update for Comet Lake, Ice Lake and Tiger Lake
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Commit Message

Liang, Kan Oct. 8, 2019, 3:50 p.m. UTC
From: Kan Liang <kan.liang@linux.intel.com>

PPERF and SMI_COUNT MSRs are also supported by Ice Lake desktop and
server.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
 arch/x86/events/msr.c | 3 +++
 1 file changed, 3 insertions(+)

Patch
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diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index c177bbe..8515512 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -92,6 +92,9 @@  static bool test_intel(int idx, void *data)
 	case INTEL_FAM6_COMETLAKE_L:
 	case INTEL_FAM6_COMETLAKE:
 	case INTEL_FAM6_ICELAKE_L:
+	case INTEL_FAM6_ICELAKE:
+	case INTEL_FAM6_ICELAKE_X:
+	case INTEL_FAM6_ICELAKE_D:
 		if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
 			return true;
 		break;