From: "tip-bot2 for Marc Zyngier" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Marc Zyngier <maz@kernel.org>, Palmer Dabbelt <palmer@sifive.com>,
Darius Rad <darius@bluespec.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
stable@vger.kernel.org, Ingo Molnar <mingo@kernel.org>,
Borislav Petkov <bp@alien8.de>,
linux-kernel@vger.kernel.org
Subject: [tip: irq/urgent] irqchip/sifive-plic: Switch to fasteoi flow
Date: Mon, 14 Oct 2019 18:38:47 -0000 [thread overview]
Message-ID: <157107832749.12254.5664038799279181370.tip-bot2@tip-bot2> (raw)
In-Reply-To: <8636gxskmj.wl-maz@kernel.org>
The following commit has been merged into the irq/urgent branch of tip:
Commit-ID: bb0fed1c60cccbe4063b455a7228818395dac86e
Gitweb: https://git.kernel.org/tip/bb0fed1c60cccbe4063b455a7228818395dac86e
Author: Marc Zyngier <maz@kernel.org>
AuthorDate: Sun, 15 Sep 2019 15:17:45 +01:00
Committer: Marc Zyngier <maz@kernel.org>
CommitterDate: Wed, 18 Sep 2019 12:29:52 +01:00
irqchip/sifive-plic: Switch to fasteoi flow
The SiFive PLIC interrupt controller seems to have all the HW
features to support the fasteoi flow, but the driver seems to be
stuck in a distant past. Bring it into the 21st century.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Tested-by: Palmer Dabbelt <palmer@sifive.com> (QEMU Boot)
Tested-by: Darius Rad <darius@bluespec.com> (on 2 HW PLIC implementations)
Tested-by: Paul Walmsley <paul.walmsley@sifive.com> (HiFive Unleashed)
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/8636gxskmj.wl-maz@kernel.org
---
drivers/irqchip/irq-sifive-plic.c | 29 +++++++++++++++--------------
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index cf75596..3e51dee 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -97,7 +97,7 @@ static inline void plic_irq_toggle(const struct cpumask *mask,
}
}
-static void plic_irq_enable(struct irq_data *d)
+static void plic_irq_unmask(struct irq_data *d)
{
unsigned int cpu = cpumask_any_and(irq_data_get_affinity_mask(d),
cpu_online_mask);
@@ -106,7 +106,7 @@ static void plic_irq_enable(struct irq_data *d)
plic_irq_toggle(cpumask_of(cpu), d->hwirq, 1);
}
-static void plic_irq_disable(struct irq_data *d)
+static void plic_irq_mask(struct irq_data *d)
{
plic_irq_toggle(cpu_possible_mask, d->hwirq, 0);
}
@@ -125,10 +125,8 @@ static int plic_set_affinity(struct irq_data *d,
if (cpu >= nr_cpu_ids)
return -EINVAL;
- if (!irqd_irq_disabled(d)) {
- plic_irq_toggle(cpu_possible_mask, d->hwirq, 0);
- plic_irq_toggle(cpumask_of(cpu), d->hwirq, 1);
- }
+ plic_irq_toggle(cpu_possible_mask, d->hwirq, 0);
+ plic_irq_toggle(cpumask_of(cpu), d->hwirq, 1);
irq_data_update_effective_affinity(d, cpumask_of(cpu));
@@ -136,14 +134,18 @@ static int plic_set_affinity(struct irq_data *d,
}
#endif
+static void plic_irq_eoi(struct irq_data *d)
+{
+ struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
+
+ writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
+}
+
static struct irq_chip plic_chip = {
.name = "SiFive PLIC",
- /*
- * There is no need to mask/unmask PLIC interrupts. They are "masked"
- * by reading claim and "unmasked" when writing it back.
- */
- .irq_enable = plic_irq_enable,
- .irq_disable = plic_irq_disable,
+ .irq_mask = plic_irq_mask,
+ .irq_unmask = plic_irq_unmask,
+ .irq_eoi = plic_irq_eoi,
#ifdef CONFIG_SMP
.irq_set_affinity = plic_set_affinity,
#endif
@@ -152,7 +154,7 @@ static struct irq_chip plic_chip = {
static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq)
{
- irq_set_chip_and_handler(irq, &plic_chip, handle_simple_irq);
+ irq_set_chip_and_handler(irq, &plic_chip, handle_fasteoi_irq);
irq_set_chip_data(irq, NULL);
irq_set_noprobe(irq);
return 0;
@@ -188,7 +190,6 @@ static void plic_handle_irq(struct pt_regs *regs)
hwirq);
else
generic_handle_irq(irq);
- writel(hwirq, claim);
}
csr_set(sie, SIE_SEIE);
}
prev parent reply other threads:[~2019-10-14 18:39 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-12 21:40 [PATCH] irqchip/sifive-plic: add irq_mask and irq_unmask Darius Rad
2019-09-14 19:00 ` Palmer Dabbelt
2019-09-14 19:42 ` Charles Papon
2019-09-14 19:51 ` Palmer Dabbelt
2019-09-15 14:24 ` Marc Zyngier
2019-09-15 17:31 ` Palmer Dabbelt
2019-09-15 18:20 ` Marc Zyngier
2019-09-15 23:46 ` Palmer Dabbelt
2019-09-16 19:04 ` Darius Rad
2019-09-16 20:51 ` Palmer Dabbelt
2019-09-16 21:33 ` Marc Zyngier
2019-09-16 22:17 ` Palmer Dabbelt
2019-09-17 12:26 ` Paul Walmsley
2019-09-20 13:28 ` David Abdurachmanov
2019-09-16 21:41 ` Darius Rad
2019-09-16 22:17 ` Palmer Dabbelt
2019-09-17 6:56 ` Christoph Hellwig
2019-10-14 18:38 ` tip-bot2 for Marc Zyngier [this message]
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