From: Kishon Vijay Abraham I <kishon@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
Roger Quadros <rogerq@ti.com>, Jyri Sarha <jsarha@ti.com>
Cc: Anil Varughese <aniljoy@cadence.com>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>
Subject: [PATCH 05/13] phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_ops
Date: Wed, 16 Oct 2019 17:01:09 +0530 [thread overview]
Message-ID: <20191016113117.12370-6-kishon@ti.com> (raw)
In-Reply-To: <20191016113117.12370-1-kishon@ti.com>
Instead of invoking cdns_sierra_phy_init() from probe, add it in
phy_ops so that it's initialized when the PHY consumer invokes
phy_init()
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 89a3b732c311..5c617248841f 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -174,7 +174,7 @@ static struct regmap_config cdns_sierra_phy_config_ctrl_config = {
.reg_read = cdns_regmap_read,
};
-static void cdns_sierra_phy_init(struct phy *gphy)
+static int cdns_sierra_phy_init(struct phy *gphy)
{
struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent);
@@ -183,6 +183,10 @@ static void cdns_sierra_phy_init(struct phy *gphy)
struct cdns_reg_pairs *vals;
u32 num_regs;
+ /* Initialise the PHY registers, unless auto configured */
+ if (phy->autoconf)
+ return 0;
+
if (ins->phy_type == PHY_TYPE_PCIE) {
num_regs = phy->init_data->pcie_regs;
vals = phy->init_data->pcie_vals;
@@ -190,7 +194,7 @@ static void cdns_sierra_phy_init(struct phy *gphy)
num_regs = phy->init_data->usb_regs;
vals = phy->init_data->usb_vals;
} else {
- return;
+ return -EINVAL;
}
for (i = 0; i < ins->num_lanes; i++) {
for (j = 0; j < num_regs ; j++) {
@@ -198,6 +202,8 @@ static void cdns_sierra_phy_init(struct phy *gphy)
regmap_write(regmap, vals[j].off, vals[j].val);
}
}
+
+ return 0;
}
static int cdns_sierra_phy_on(struct phy *gphy)
@@ -216,6 +222,7 @@ static int cdns_sierra_phy_off(struct phy *gphy)
}
static const struct phy_ops ops = {
+ .init = cdns_sierra_phy_init,
.power_on = cdns_sierra_phy_on,
.power_off = cdns_sierra_phy_off,
.owner = THIS_MODULE,
@@ -436,10 +443,6 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev)
sp->phys[node].phy = gphy;
phy_set_drvdata(gphy, &sp->phys[node]);
- /* Initialise the PHY registers, unless auto configured */
- if (!sp->autoconf)
- cdns_sierra_phy_init(gphy);
-
node++;
}
sp->nsubnodes = node;
--
2.17.1
next prev parent reply other threads:[~2019-10-16 11:32 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-16 11:31 [PATCH 00/13] PHY: Add support for SERDES in TI's J721E SoC Kishon Vijay Abraham I
2019-10-16 11:31 ` [PATCH 01/13] dt-bindings: phy: Sierra: Add bindings for Sierra in TI's J721E Kishon Vijay Abraham I
2019-10-16 11:31 ` [PATCH 02/13] phy: cadence: Sierra: Make "phy_clk" and "sierra_apb" optional resources Kishon Vijay Abraham I
2019-10-16 11:31 ` [PATCH 03/13] phy: cadence: Sierra: Use "regmap" for read and write to Sierra registers Kishon Vijay Abraham I
2019-10-16 11:31 ` [PATCH 04/13] phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoC Kishon Vijay Abraham I
2019-10-16 11:31 ` Kishon Vijay Abraham I [this message]
2019-10-16 11:31 ` [PATCH 06/13] phy: cadence: Sierra: Modify register macro names to be in sync with Sierra user guide Kishon Vijay Abraham I
2019-10-16 11:31 ` [PATCH 07/13] phy: cadence: Sierra: Configure both lane cdb and common cdb registers for external SSC Kishon Vijay Abraham I
2019-10-16 11:31 ` [PATCH 08/13] phy: cadence: Sierra: Get reset control "array" for each link Kishon Vijay Abraham I
2019-10-16 11:31 ` [PATCH 09/13] phy: cadence: Sierra: Check for PLL lock during PHY power on Kishon Vijay Abraham I
2019-10-16 11:31 ` [PATCH 10/13] phy: cadence: Sierra: Change MAX_LANES of Sierra to 16 Kishon Vijay Abraham I
2019-10-16 11:31 ` [PATCH 11/13] phy: cadence: Sierra: Set cmn_refclk/cmn_refclk1 frequency to 25MHz Kishon Vijay Abraham I
2019-10-16 11:31 ` [PATCH 12/13] dt-bindings: phy: Document WIZ (SERDES wrapper) bindings Kishon Vijay Abraham I
2019-10-16 11:31 ` [PATCH 13/13] phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC Kishon Vijay Abraham I
2019-10-22 13:05 ` [PATCH 00/13] PHY: Add support for SERDES in TI's " Roger Quadros
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