From: <Tudor.Ambarus@microchip.com>
To: <miquel.raynal@bootlin.com>, <richard@nod.at>, <vigneshr@ti.com>,
<boris.brezillon@collabora.com>
Cc: <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
<Tudor.Ambarus@microchip.com>
Subject: [PATCH v3 30/32] mtd: spi-nor: Rename macronix_quad_enable to spi_nor_sr1_bit6_quad_enable
Date: Tue, 29 Oct 2019 11:17:37 +0000 [thread overview]
Message-ID: <20191029111615.3706-31-tudor.ambarus@microchip.com> (raw)
In-Reply-To: <20191029111615.3706-1-tudor.ambarus@microchip.com>
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Rename method to a generic name: spi_nor_sr1_bit6_quad_enable().
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 19 +++++++++----------
include/linux/mtd/spi-nor.h | 2 +-
2 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index ab028afc503f..47d159959461 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -2078,16 +2078,15 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
}
/**
- * macronix_quad_enable() - set QE bit in Status Register.
+ * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status
+ * Register 1.
* @nor: pointer to a 'struct spi_nor'
*
- * Set the Quad Enable (QE) bit in the Status Register.
- *
- * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
+ * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories.
*
* Return: 0 on success, -errno otherwise.
*/
-static int macronix_quad_enable(struct spi_nor *nor)
+static int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor)
{
int ret;
@@ -2095,10 +2094,10 @@ static int macronix_quad_enable(struct spi_nor *nor)
if (ret)
return ret;
- if (nor->bouncebuf[0] & SR_QUAD_EN_MX)
+ if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)
return 0;
- nor->bouncebuf[0] |= SR_QUAD_EN_MX;
+ nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6;
return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]);
}
@@ -2349,7 +2348,7 @@ static void gd25q256_default_init(struct spi_nor *nor)
* indicate the quad_enable method for this case, we need
* to set it in the default_init fixup hook.
*/
- nor->params.quad_enable = macronix_quad_enable;
+ nor->params.quad_enable = spi_nor_sr1_bit6_quad_enable;
}
static struct spi_nor_fixups gd25q256_fixups = {
@@ -3729,7 +3728,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
case BFPT_DWORD15_QER_SR1_BIT6:
nor->flags &= ~SNOR_F_HAS_16BIT_SR;
- params->quad_enable = macronix_quad_enable;
+ params->quad_enable = spi_nor_sr1_bit6_quad_enable;
break;
case BFPT_DWORD15_QER_SR2_BIT7:
@@ -4627,7 +4626,7 @@ static int spi_nor_setup(struct spi_nor *nor,
static void macronix_set_default_init(struct spi_nor *nor)
{
- nor->params.quad_enable = macronix_quad_enable;
+ nor->params.quad_enable = spi_nor_sr1_bit6_quad_enable;
nor->params.set_4byte = macronix_set_4byte;
}
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index f626e0e52909..6d703df97f13 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -133,7 +133,7 @@
#define SR_E_ERR BIT(5)
#define SR_P_ERR BIT(6)
-#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
+#define SR1_QUAD_EN_BIT6 BIT(6)
/* Enhanced Volatile Configuration Register bits */
#define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
--
2.9.5
next prev parent reply other threads:[~2019-10-29 11:18 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-29 11:16 [PATCH v3 00/32] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
2019-10-29 11:16 ` [PATCH v3 01/32] mtd: spi-nor: Prepend spi_nor_ to all Reg Ops methods Tudor.Ambarus
2019-10-31 10:34 ` Boris Brezillon
2019-11-02 10:34 ` Tudor.Ambarus
2019-10-29 11:16 ` [PATCH v3 02/32] mtd: spi-nor: Drop duplicated new line Tudor.Ambarus
2019-10-31 10:34 ` Boris Brezillon
2019-11-02 10:34 ` Tudor.Ambarus
2019-10-29 11:16 ` [PATCH v3 03/32] mtd: spi-nor: Group all Reg Ops to avoid forward declarations Tudor.Ambarus
2019-10-31 10:35 ` Boris Brezillon
2019-11-02 10:35 ` Tudor.Ambarus
2019-10-29 11:16 ` [PATCH v3 04/32] mtd: spi-nor: Stop compare with negative in Reg Ops methods Tudor.Ambarus
2019-10-31 10:36 ` Boris Brezillon
2019-11-02 10:36 ` Tudor.Ambarus
2019-10-29 11:16 ` [PATCH v3 05/32] mtd: spi-nor: Drop explicit cast to int to already int value Tudor.Ambarus
2019-10-31 10:36 ` Boris Brezillon
2019-11-02 10:37 ` Tudor.Ambarus
2019-10-29 11:16 ` [PATCH v3 06/32] mtd: spi-nor: Use dev_err() instead of pr_err() Tudor.Ambarus
2019-10-31 10:43 ` Boris Brezillon
2019-11-02 10:38 ` Tudor.Ambarus
2019-10-29 11:16 ` [PATCH v3 07/32] mtd: spi-nor: Don't overwrite errno from Reg Ops Tudor.Ambarus
2019-10-31 10:48 ` Boris Brezillon
2019-11-02 10:39 ` Tudor.Ambarus
2019-10-29 11:17 ` [PATCH v3 08/32] mtd: spi-nor: Pointer parameter for SR in spi_nor_read_sr() Tudor.Ambarus
2019-10-31 10:51 ` Boris Brezillon
2019-11-02 10:42 ` Tudor.Ambarus
2019-10-29 11:17 ` [PATCH v3 09/32] mtd: spi-nor: Pointer parameter for FSR in spi_nor_read_fsr() Tudor.Ambarus
2019-10-31 10:53 ` Boris Brezillon
2019-11-02 10:44 ` Tudor.Ambarus
2019-10-29 11:17 ` [PATCH v3 10/32] mtd: spi-nor: Pointer parameter for CR in spi_nor_read_cr() Tudor.Ambarus
2019-10-31 10:58 ` Boris Brezillon
2019-10-31 14:26 ` Tudor.Ambarus
2019-11-02 10:45 ` Tudor.Ambarus
2019-10-29 11:17 ` [PATCH v3 11/32] mtd: spi-nor: Drop redundant error reports in Reg Ops callers Tudor.Ambarus
2019-10-31 10:59 ` Boris Brezillon
2019-11-02 10:46 ` Tudor.Ambarus
2019-10-29 11:17 ` [PATCH v3 12/32] mtd: spi-nor: Void return type for spi_nor_clear_sr/fsr() Tudor.Ambarus
2019-10-31 11:02 ` Boris Brezillon
2019-10-29 11:17 ` [PATCH v3 13/32] mtd: spi-nor: Print error messages inside Reg Ops methods Tudor.Ambarus
2019-10-31 11:05 ` Boris Brezillon
2019-10-31 14:18 ` Tudor.Ambarus
2019-10-29 11:17 ` [PATCH v3 14/32] mtd: spi-nor: Fix retlen handling in sst_write() Tudor.Ambarus
2019-10-31 11:12 ` Boris Brezillon
2019-11-02 10:47 ` Tudor.Ambarus
2019-10-29 11:17 ` [PATCH v3 15/32] mtd: spi-nor: Check for errors after each Register Operation Tudor.Ambarus
2019-10-31 6:57 ` Tudor.Ambarus
2019-10-29 11:17 ` [PATCH v3 16/32] mtd: spi-nor: Rename label as it is no longer generic Tudor.Ambarus
2019-10-31 11:14 ` Boris Brezillon
2019-10-29 11:17 ` [PATCH v3 17/32] mtd: spi-nor: Move the WE and wait calls inside Write SR methods Tudor.Ambarus
2019-10-31 11:15 ` Boris Brezillon
2019-10-29 11:17 ` [PATCH v3 18/32] mtd: spi-nor: Constify data to write to the Status Register Tudor.Ambarus
2019-10-31 11:16 ` Boris Brezillon
2019-11-02 10:48 ` Tudor.Ambarus
2019-10-29 11:17 ` [PATCH v3 19/32] mtd: spi-nor: Merge spi_nor_write_sr() and spi_nor_write_sr_cr() Tudor.Ambarus
2019-10-31 11:17 ` Boris Brezillon
2019-10-29 11:17 ` [PATCH v3 20/32] mtd: spi-nor: Describe all the Reg Ops Tudor.Ambarus
2019-10-29 11:17 ` [PATCH v3 21/32] mtd: spi-nor: Drop spansion_quad_enable() Tudor.Ambarus
2019-10-29 11:17 ` [PATCH v3 22/32] mtd: spi-nor: Fix errno on Quad Enable methods Tudor.Ambarus
2019-10-29 11:17 ` [PATCH v3 23/32] mtd: spi-nor: Check all the bits written, not just the BP ones Tudor.Ambarus
2019-10-29 11:17 ` [PATCH v3 24/32] mtd: spi-nor: Print error message when the read back test fails Tudor.Ambarus
2019-10-29 11:17 ` [PATCH v3 25/32] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock() Tudor.Ambarus
2019-10-29 11:17 ` [PATCH v3 26/32] mtd: spi-nor: Extend the QE Read Back test to the entire SR byte Tudor.Ambarus
2019-10-29 11:17 ` [PATCH v3 27/32] mtd: spi-nor: Extend the QE Read Back test to both SR1 and SR2 Tudor.Ambarus
2019-10-29 11:17 ` [PATCH v3 28/32] mtd: spi-nor: Rename CR_QUAD_EN_SPAN to SR2_QUAD_EN_BIT1 Tudor.Ambarus
2019-10-29 11:17 ` [PATCH v3 29/32] mtd: spi-nor: Merge spansion Quad Enable methods Tudor.Ambarus
2019-10-29 11:17 ` Tudor.Ambarus [this message]
2019-10-29 11:17 ` [PATCH v3 31/32] mtd: spi-nor: Prepend "spi_nor_" to "sr2_bit7_quad_enable" Tudor.Ambarus
2019-10-29 11:17 ` [PATCH v3 32/32] mtd: spi-nor: Rework the disabling of block write protection Tudor.Ambarus
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20191029111615.3706-31-tudor.ambarus@microchip.com \
--to=tudor.ambarus@microchip.com \
--cc=boris.brezillon@collabora.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mtd@lists.infradead.org \
--cc=miquel.raynal@bootlin.com \
--cc=richard@nod.at \
--cc=vigneshr@ti.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).