From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
To: gregkh@linuxfoundation.org
Cc: linux-kernel@vger.kernel.org, Heiko Stuebner <heiko@sntech.de>,
Rob Herring <robh@kernel.org>,
Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Subject: [PATCH 09/10] dt-bindings: nvmem: add binding for Rockchip OTP controller
Date: Tue, 29 Oct 2019 11:42:39 +0000 [thread overview]
Message-ID: <20191029114240.14905-10-srinivas.kandagatla@linaro.org> (raw)
In-Reply-To: <20191029114240.14905-1-srinivas.kandagatla@linaro.org>
From: Heiko Stuebner <heiko@sntech.de>
Newer Rockchip SoCs use a different IP for accessing special one-
time-programmable memory, so add a binding for these controllers.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
.../bindings/nvmem/rockchip-otp.txt | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
create mode 100644 Documentation/devicetree/bindings/nvmem/rockchip-otp.txt
diff --git a/Documentation/devicetree/bindings/nvmem/rockchip-otp.txt b/Documentation/devicetree/bindings/nvmem/rockchip-otp.txt
new file mode 100644
index 000000000000..40f649f7c2e5
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/rockchip-otp.txt
@@ -0,0 +1,25 @@
+Rockchip internal OTP (One Time Programmable) memory device tree bindings
+
+Required properties:
+- compatible: Should be one of the following.
+ - "rockchip,px30-otp" - for PX30 SoCs.
+ - "rockchip,rk3308-otp" - for RK3308 SoCs.
+- reg: Should contain the registers location and size
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Should be "otp", "apb_pclk" and "phy".
+- resets: Must contain an entry for each entry in reset-names.
+ See ../../reset/reset.txt for details.
+- reset-names: Should be "phy".
+
+See nvmem.txt for more information.
+
+Example:
+ otp: otp@ff290000 {
+ compatible = "rockchip,px30-otp";
+ reg = <0x0 0xff290000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
+ <&cru PCLK_OTP_PHY>;
+ clock-names = "otp", "apb_pclk", "phy";
+ };
--
2.21.0
next prev parent reply other threads:[~2019-10-29 11:43 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-29 11:42 [PATCH 00/10] nvmem: patches(set 1) for 5.5 Srinivas Kandagatla
2019-10-29 11:42 ` [PATCH 01/10] nvmem: core: fix nvmem_cell_write inline function Srinivas Kandagatla
2019-10-29 11:42 ` [PATCH 02/10] nvmem: sc27xx: Change to use devm_hwspin_lock_request_specific() to request one hwlock Srinivas Kandagatla
2019-10-29 11:42 ` [PATCH 03/10] nvmem: imx: scu: support hole region check Srinivas Kandagatla
2019-10-29 11:42 ` [PATCH 04/10] nvmem: imx: scu: support write Srinivas Kandagatla
2019-10-29 11:42 ` [PATCH 05/10] nvmem: imx-ocotp: reset error status on probe Srinivas Kandagatla
2019-10-29 11:42 ` [PATCH 06/10] dt-bindings: nvmem: Add Spreadtrum eFuse controller documentation Srinivas Kandagatla
2019-10-29 11:42 ` [PATCH 07/10] nvmem: sprd: Add Spreadtrum SoCs eFuse support Srinivas Kandagatla
2019-10-29 11:42 ` [PATCH 08/10] nvmem: imx: scu: fix dependency in Kconfig Srinivas Kandagatla
2019-10-29 11:42 ` Srinivas Kandagatla [this message]
2019-10-29 11:42 ` [PATCH 10/10] nvmem: add Rockchip OTP driver Srinivas Kandagatla
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