From: Can Guo <cang@codeaurora.org>
To: asutoshd@codeaurora.org, nguyenb@codeaurora.org,
rnayak@codeaurora.org, linux-scsi@vger.kernel.org,
kernel-team@android.com, saravanak@google.com,
salyzyn@google.com, cang@codeaurora.org
Cc: Alim Akhtar <alim.akhtar@samsung.com>,
Avri Altman <avri.altman@wdc.com>,
Pedro Sousa <pedrom.sousa@synopsys.com>,
"James E.J. Bottomley" <jejb@linux.ibm.com>,
"Martin K. Petersen" <martin.petersen@oracle.com>,
Tomas Winkler <tomas.winkler@intel.com>,
Stanley Chu <stanley.chu@mediatek.com>,
Subhash Jadavani <subhashj@codeaurora.org>,
Venkat Gopalakrishnan <venkatg@codeaurora.org>,
linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v2 5/6] scsi: ufs: Add dev ref clock gating wait time support
Date: Thu, 7 Nov 2019 01:47:56 -0800 [thread overview]
Message-ID: <1573120078-15547-6-git-send-email-cang@codeaurora.org> (raw)
In-Reply-To: <1573120078-15547-1-git-send-email-cang@codeaurora.org>
In UFS version 3.0, a newly added attribute bRefClkGatingWaitTime defines
the minimum time for which the reference clock is required by device during
transition to LS-MODE or HIBERN8 state. Make this change to reflect the new
requirement by adding delays before turning off the clock.
Signed-off-by: Can Guo <cang@codeaurora.org>
---
drivers/scsi/ufs/ufs.h | 3 +++
drivers/scsi/ufs/ufshcd.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 49 insertions(+)
diff --git a/drivers/scsi/ufs/ufs.h b/drivers/scsi/ufs/ufs.h
index 3327981..385bac8 100644
--- a/drivers/scsi/ufs/ufs.h
+++ b/drivers/scsi/ufs/ufs.h
@@ -168,6 +168,7 @@ enum attr_idn {
QUERY_ATTR_IDN_FFU_STATUS = 0x14,
QUERY_ATTR_IDN_PSA_STATE = 0x15,
QUERY_ATTR_IDN_PSA_DATA_SIZE = 0x16,
+ QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME = 0x17,
};
/* Descriptor idn for Query requests */
@@ -530,6 +531,8 @@ struct ufs_dev_info {
bool f_power_on_wp_en;
/* Keeps information if any of the LU is power on write protected */
bool is_lu_power_on_wp;
+ u16 spec_version;
+ u32 clk_gating_wait_us;
};
#define MAX_MODEL_LEN 16
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 4dfd705..d2d56f8 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -91,6 +91,9 @@
/* default delay of autosuspend: 2000 ms */
#define RPM_AUTOSUSPEND_DELAY_MS 2000
+/* Default value of wait time before gating device ref clock */
+#define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */
+
#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
({ \
int _ret; \
@@ -3352,6 +3355,37 @@ static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
param_offset, param_read_buf, param_size);
}
+static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba)
+{
+ int err = 0;
+ u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
+
+ if (hba->dev_info.spec_version >= 0x300) {
+ err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
+ QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0,
+ &gating_wait);
+ if (err)
+ dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n",
+ err, gating_wait);
+
+ if (gating_wait == 0) {
+ gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
+ dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n",
+ gating_wait);
+ }
+
+ /*
+ * bRefClkGatingWaitTime defines the minimum time for which the
+ * reference clock is required by device during transition from
+ * HS-MODE to LS-MODE or HIBERN8 state. Give it more time to be
+ * on the safe side.
+ */
+ hba->dev_info.clk_gating_wait_us = gating_wait + 50;
+ }
+
+ return err;
+}
+
/**
* ufshcd_memory_alloc - allocate memory for host memory space data structures
* @hba: per adapter instance
@@ -6623,6 +6657,10 @@ static int ufs_get_device_desc(struct ufs_hba *hba,
dev_desc->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
+ /* getting Specification Version in big endian format */
+ hba->dev_info.spec_version = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 |
+ desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1];
+
model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
err = ufshcd_read_string_desc(hba, model_index,
&dev_desc->model, SD_ASCII_STD);
@@ -7041,6 +7079,9 @@ static int ufshcd_probe_hba(struct ufs_hba *hba)
/* clear any previous UFS device information */
memset(&hba->dev_info, 0, sizeof(hba->dev_info));
+
+ ufshcd_get_ref_clk_gating_wait(hba);
+
if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
hba->dev_info.f_power_on_wp_en = flag;
@@ -7373,12 +7414,17 @@ static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
struct ufs_clk_info *clki;
struct list_head *head = &hba->clk_list_head;
unsigned long flags;
+ unsigned long gating_wait;
ktime_t start = ktime_get();
bool clk_state_changed = false;
if (list_empty(head))
goto out;
+ gating_wait = (unsigned long)hba->dev_info.clk_gating_wait_us;
+ if (!on && !skip_ref_clk && !!gating_wait)
+ usleep_range(gating_wait, gating_wait + 10);
+
ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
if (ret)
return ret;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2019-11-07 9:49 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1573120078-15547-1-git-send-email-cang@codeaurora.org>
2019-11-07 9:47 ` [PATCH v2 1/6] scsi: ufs: Flush exception event before suspend Can Guo
2019-11-07 9:47 ` [PATCH v2 2/6] scsi: ufs: set load before setting voltage in regulators Can Guo
2019-11-07 9:47 ` [PATCH v2 3/6] scsi: ufs: Remove the check before call setup clock notify vops Can Guo
2019-11-07 9:47 ` [PATCH v2 4/6] scsi: ufs-qcom: Adjust bus bandwidth voting and unvoting Can Guo
2019-11-07 9:47 ` Can Guo [this message]
2019-11-07 9:47 ` [PATCH v2 6/6] scsi: ufs: Fix ufshcd_hold() caused scheduling while atomic Can Guo
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