From: "tip-bot2 for Andrea Parri" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Andrea Parri <parri.andrea@gmail.com>,
Thomas Gleixner <tglx@linutronix.de>,
Michael Kelley <mikelley@microsoft.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Ingo Molnar <mingo@kernel.org>, Borislav Petkov <bp@alien8.de>,
linux-kernel@vger.kernel.org
Subject: [tip: x86/hyperv] x86/hyperv: Allow guests to enable InvariantTSC
Date: Tue, 12 Nov 2019 10:50:02 -0000 [thread overview]
Message-ID: <157355580216.29376.5207364580446998985.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20191003155200.22022-1-parri.andrea@gmail.com>
The following commit has been merged into the x86/hyperv branch of tip:
Commit-ID: dce7cd62754b5d4a6e401b8b0769ec94cf971041
Gitweb: https://git.kernel.org/tip/dce7cd62754b5d4a6e401b8b0769ec94cf971041
Author: Andrea Parri <parri.andrea@gmail.com>
AuthorDate: Thu, 03 Oct 2019 17:52:00 +02:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Tue, 12 Nov 2019 11:44:21 +01:00
x86/hyperv: Allow guests to enable InvariantTSC
If the hardware supports TSC scaling, Hyper-V will set bit 15 of the
HV_PARTITION_PRIVILEGE_MASK in guest VMs with a compatible Hyper-V
configuration version. Bit 15 corresponds to the
AccessTscInvariantControls privilege. If this privilege bit is set,
guests can access the HvSyntheticInvariantTscControl MSR: guests can
set bit 0 of this synthetic MSR to enable the InvariantTSC feature.
After setting the synthetic MSR, CPUID will enumerate support for
InvariantTSC.
Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Michael Kelley <mikelley@microsoft.com>
Reviewed-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Link: https://lkml.kernel.org/r/20191003155200.22022-1-parri.andrea@gmail.com
---
arch/x86/include/asm/hyperv-tlfs.h | 5 +++++
arch/x86/kernel/cpu/mshyperv.c | 7 ++++++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/hyperv-tlfs.h b/arch/x86/include/asm/hyperv-tlfs.h
index 7a27056..887b1d6 100644
--- a/arch/x86/include/asm/hyperv-tlfs.h
+++ b/arch/x86/include/asm/hyperv-tlfs.h
@@ -86,6 +86,8 @@
#define HV_X64_ACCESS_FREQUENCY_MSRS BIT(11)
/* AccessReenlightenmentControls privilege */
#define HV_X64_ACCESS_REENLIGHTENMENT BIT(13)
+/* AccessTscInvariantControls privilege */
+#define HV_X64_ACCESS_TSC_INVARIANT BIT(15)
/*
* Feature identification: indicates which flags were specified at partition
@@ -270,6 +272,9 @@
#define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107
#define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108
+/* TSC invariant control */
+#define HV_X64_MSR_TSC_INVARIANT_CONTROL 0x40000118
+
/*
* Declare the MSR used to setup pages used to communicate with the hypervisor.
*/
diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c
index 062f772..6f7c822 100644
--- a/arch/x86/kernel/cpu/mshyperv.c
+++ b/arch/x86/kernel/cpu/mshyperv.c
@@ -285,7 +285,12 @@ static void __init ms_hyperv_init_platform(void)
machine_ops.shutdown = hv_machine_shutdown;
machine_ops.crash_shutdown = hv_machine_crash_shutdown;
#endif
- mark_tsc_unstable("running on Hyper-V");
+ if (ms_hyperv.features & HV_X64_ACCESS_TSC_INVARIANT) {
+ wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, 0x1);
+ setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
+ } else {
+ mark_tsc_unstable("running on Hyper-V");
+ }
/*
* Generation 2 instances don't support reading the NMI status from
prev parent reply other threads:[~2019-11-12 10:50 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-03 15:52 [PATCH 1/2] x86/hyperv: Allow guests to enable InvariantTSC Andrea Parri
2019-10-03 16:03 ` Andrea Parri
2019-10-03 23:15 ` Michael Kelley
2019-10-04 16:57 ` Vitaly Kuznetsov
2019-10-04 22:05 ` Michael Kelley
2019-10-08 15:12 ` Vitaly Kuznetsov
2019-11-12 10:50 ` tip-bot2 for Andrea Parri [this message]
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