From: Peng Fan <peng.fan@nxp.com>
To: "sboyd@kernel.org" <sboyd@kernel.org>,
"shawnguo@kernel.org" <shawnguo@kernel.org>,
"s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
"festevam@gmail.com" <festevam@gmail.com>,
Abel Vesa <abel.vesa@nxp.com>
Cc: "kernel@pengutronix.de" <kernel@pengutronix.de>,
dl-linux-imx <linux-imx@nxp.com>,
Aisheng Dong <aisheng.dong@nxp.com>,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Leonard Crestez <leonard.crestez@nxp.com>,
Alice Guo <alice.guo@nxp.com>, Peng Fan <peng.fan@nxp.com>
Subject: [PATCH 1/2] clk: imx: sccg: use relaxed io api
Date: Wed, 13 Nov 2019 10:02:03 +0000 [thread overview]
Message-ID: <1573638817-4363-1-git-send-email-peng.fan@nxp.com> (raw)
From: Peng Fan <peng.fan@nxp.com>
It is ok to use relaxed api here, no need to use stronger readl/writel
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk-sccg-pll.c | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c
index 2cf874813458..e03f8acb1e82 100644
--- a/drivers/clk/imx/clk-sccg-pll.c
+++ b/drivers/clk/imx/clk-sccg-pll.c
@@ -106,8 +106,9 @@ static int clk_sccg_pll_wait_lock(struct clk_sccg_pll *pll)
/* don't wait for lock if all plls are bypassed */
if (!(val & SSCG_PLL_BYPASS2_MASK))
- return readl_poll_timeout(pll->base, val, val & PLL_LOCK_MASK,
- 0, PLL_SCCG_LOCK_TIMEOUT);
+ return readl_relaxed_poll_timeout(pll->base, val,
+ val & PLL_LOCK_MASK,
+ 0, PLL_SCCG_LOCK_TIMEOUT);
return 0;
}
@@ -349,7 +350,7 @@ static unsigned long clk_sccg_pll_recalc_rate(struct clk_hw *hw,
temp64 = parent_rate;
- val = readl(pll->base + PLL_CFG0);
+ val = readl_relaxed(pll->base + PLL_CFG0);
if (val & SSCG_PLL_BYPASS2_MASK) {
temp64 = parent_rate;
} else if (val & SSCG_PLL_BYPASS1_MASK) {
@@ -372,10 +373,10 @@ static int clk_sccg_pll_set_rate(struct clk_hw *hw, unsigned long rate,
u32 val;
/* set bypass here too since the parent might be the same */
- val = readl(pll->base + PLL_CFG0);
+ val = readl_relaxed(pll->base + PLL_CFG0);
val &= ~SSCG_PLL_BYPASS_MASK;
val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, setup->bypass);
- writel(val, pll->base + PLL_CFG0);
+ writel_relaxed(val, pll->base + PLL_CFG0);
val = readl_relaxed(pll->base + PLL_CFG2);
val &= ~(PLL_DIVF1_MASK | PLL_DIVF2_MASK);
@@ -396,7 +397,7 @@ static u8 clk_sccg_pll_get_parent(struct clk_hw *hw)
u32 val;
u8 ret = pll->parent;
- val = readl(pll->base + PLL_CFG0);
+ val = readl_relaxed(pll->base + PLL_CFG0);
if (val & SSCG_PLL_BYPASS2_MASK)
ret = pll->bypass2;
else if (val & SSCG_PLL_BYPASS1_MASK)
@@ -409,10 +410,10 @@ static int clk_sccg_pll_set_parent(struct clk_hw *hw, u8 index)
struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
u32 val;
- val = readl(pll->base + PLL_CFG0);
+ val = readl_relaxed(pll->base + PLL_CFG0);
val &= ~SSCG_PLL_BYPASS_MASK;
val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, pll->setup.bypass);
- writel(val, pll->base + PLL_CFG0);
+ writel_relaxed(val, pll->base + PLL_CFG0);
return clk_sccg_pll_wait_lock(pll);
}
--
2.16.4
next reply other threads:[~2019-11-13 10:02 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-13 10:02 Peng Fan [this message]
2019-11-13 10:02 ` [PATCH 2/2] clk: imx: composite-8m: use relaxed io api Peng Fan
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