tools/power/x86/intel-speed-select: Display TRL buckets for just base config level
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Message ID 20191120002254.13842-1-srinivas.pandruvada@linux.intel.com
State Accepted
Commit 1434a3d357d656d4b11fcbdc9b6c35dc673292a0
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  • tools/power/x86/intel-speed-select: Display TRL buckets for just base config level
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Commit Message

Srinivas Pandruvada Nov. 20, 2019, 12:22 a.m. UTC
When only base config level is present, this tool is displaying TRL
(Turbo-ratio-limits) by reading legacy MSR. In this case, also present
core count for TRL by reading MSR 0x1AE.

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
---
 tools/power/x86/intel-speed-select/isst-core.c | 1 +
 1 file changed, 1 insertion(+)

Patch
diff mbox series

diff --git a/tools/power/x86/intel-speed-select/isst-core.c b/tools/power/x86/intel-speed-select/isst-core.c
index aa19c9998e6c..d14c7bcd327a 100644
--- a/tools/power/x86/intel-speed-select/isst-core.c
+++ b/tools/power/x86/intel-speed-select/isst-core.c
@@ -681,6 +681,7 @@  int isst_get_process_ctdp(int cpu, int tdp_level, struct isst_pkg_ctdp *pkg_dev)
 			}
 
 			isst_get_get_trl_from_msr(cpu, ctdp_level->trl_sse_active_cores);
+			isst_get_trl_bucket_info(cpu, &ctdp_level->buckets_info);
 			continue;
 		}