From: Huazhong Tan <tanhuazhong@huawei.com>
To: <davem@davemloft.net>
Cc: <netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<salil.mehta@huawei.com>, <yisen.zhuang@huawei.com>,
<linuxarm@huawei.com>, <jakub.kicinski@netronome.com>,
Huazhong Tan <tanhuazhong@huawei.com>
Subject: [PATCH V2 net] net: hns3: fix a wrong reset interrupt status mask
Date: Wed, 20 Nov 2019 10:07:15 +0800 [thread overview]
Message-ID: <1574215635-43836-1-git-send-email-tanhuazhong@huawei.com> (raw)
According to hardware user manual, bits5~7 in register
HCLGE_MISC_VECTOR_INT_STS means reset interrupts status,
but HCLGE_RESET_INT_M is defined as bits0~2 now. So it
will make hclge_reset_err_handle() read the wrong reset
interrupt status.
This patch fixes this wrong bit mask.
Fixes: 2336f19d7892 ("net: hns3: check reset interrupt status when reset fails")
Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
---
Change log:
V1->V2: fixes comment from David Miller.
---
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
index 59b8243..615cde1 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
@@ -166,7 +166,7 @@ enum HLCGE_PORT_TYPE {
#define HCLGE_GLOBAL_RESET_BIT 0
#define HCLGE_CORE_RESET_BIT 1
#define HCLGE_IMP_RESET_BIT 2
-#define HCLGE_RESET_INT_M GENMASK(2, 0)
+#define HCLGE_RESET_INT_M GENMASK(7, 5)
#define HCLGE_FUN_RST_ING 0x20C00
#define HCLGE_FUN_RST_ING_B 0
--
2.7.4
next reply other threads:[~2019-11-20 2:06 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-20 2:07 Huazhong Tan [this message]
2019-11-20 3:11 ` [PATCH V2 net] net: hns3: fix a wrong reset interrupt status mask David Miller
-- strict thread matches above, loose matches on Subject: below --
2019-11-20 1:44 Huazhong Tan
2019-11-20 1:48 ` tanhuazhong
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