From: Ran Wang <ran.wang_1@nxp.com>
To: Rob Herring <robh+dt@kernel.org>, Felipe Balbi <balbi@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Mark Rutland <mark.rutland@arm.com>
Cc: Peter Chen <peter.chen@nxp.com>, Jun Li <jun.li@nxp.com>,
Leo Li <leoyang.li@nxp.com>,
linux-usb@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Ran Wang <ran.wang_1@nxp.com>
Subject: [PATCH v3 1/2] usb: dwc3: Add chip-specific compatible string
Date: Thu, 21 Nov 2019 10:42:05 +0800 [thread overview]
Message-ID: <20191121024206.32933-1-ran.wang_1@nxp.com> (raw)
Some Layerscape paltforms (such as LS1088A, LS2088A, etc) require update HW
default cache type configuration to fix DWC3 init failure when applying
property dma-coherent.
Note that the cache type configuration is actually native feature of DWC3,
not additional desgin coming from SoC, so add this support here.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
Change in v3:
- Update commit subject according to content change, originanl one is
'usb: dwc3: Add node to update cache type setting'
- Replace sub-node definition with chip-specifc compatible string.
Change in v2:
- New file.
Documentation/devicetree/bindings/usb/dwc3.txt | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 66780a4..043c312e 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -4,7 +4,21 @@ DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
as described in 'usb/generic.txt'
Required properties:
- - compatible: must be "snps,dwc3"
+ - compatible: must be "snps,dwc3" and (if applicable) may contain a
+ chip-specific compatible string in front of it to allow dwc3 driver be
+ able to update cache type configuration accordingly, otherwise
+ Layerscape SoC will encounter USB init failure when adding property
+ dma-coherent on device tree.
+ Example:
+ * "fsl,ls1012a-dwc3", "snps,dwc3"
+ * "fsl,ls1021a-dwc3", "snps,dwc3"
+ * "fsl,ls1028a-dwc3", "snps,dwc3"
+ * "fsl,ls1043a-dwc3", "snps,dwc3"
+ * "fsl,ls1046a-dwc3", "snps,dwc3"
+ * "fsl,ls1088a-dwc3", "snps,dwc3"
+ * "fsl,ls2088a-dwc3", "snps,dwc3"
+ * "fsl,lx2160a-dwc3", "snps,dwc3"
+
- reg : Address and length of the register set for the device
- interrupts: Interrupts used by the dwc3 controller.
- clock-names: should contain "ref", "bus_early", "suspend"
--
2.7.4
next reply other threads:[~2019-11-21 2:42 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-21 2:42 Ran Wang [this message]
2019-11-21 2:42 ` [PATCH v3 2/2] usb: dwc3: Add cache type configuration support Ran Wang
2019-11-21 9:54 ` Peter Chen
2019-11-23 0:46 ` [PATCH v3 1/2] usb: dwc3: Add chip-specific compatible string Rob Herring
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