From: Abel Vesa <abel.vesa@nxp.com>
To: Shawn Guo <shawnguo@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
Sascha Hauer <kernel@pengutronix.de>
Cc: Dong Aisheng <aisheng.dong@nxp.com>,
NXP Linux Team <linux-imx@nxp.com>, Peng Fan <peng.fan@nxp.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
Leonard Crestez <leonard.crestez@nxp.com>,
Jacky Bai <ping.bai@nxp.com>, Abel Vesa <abel.vesa@nxp.com>
Subject: [RESEND v2 09/11] clk: imx: Rename the imx_clk_pfdv2 to imply it's clk_hw based
Date: Wed, 11 Dec 2019 11:25:48 +0200 [thread overview]
Message-ID: <1576056350-20715-10-git-send-email-abel.vesa@nxp.com> (raw)
In-Reply-To: <1576056350-20715-1-git-send-email-abel.vesa@nxp.com>
Renaming the imx_clk_pfdv2 register function to imx_clk_hw_pfdv2 to be
more obvious it is clk_hw based.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk-imx7ulp.c | 16 ++++++++--------
drivers/clk/imx/clk-pfdv2.c | 2 +-
drivers/clk/imx/clk.h | 2 +-
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c
index 48bad87..88510f3 100644
--- a/drivers/clk/imx/clk-imx7ulp.c
+++ b/drivers/clk/imx/clk-imx7ulp.c
@@ -94,16 +94,16 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np)
clks[IMX7ULP_CLK_SPLL] = imx_clk_hw_pllv4("spll", "spll_pre_div", base + 0x600);
/* APLL PFDs */
- clks[IMX7ULP_CLK_APLL_PFD0] = imx_clk_pfdv2("apll_pfd0", "apll", base + 0x50c, 0);
- clks[IMX7ULP_CLK_APLL_PFD1] = imx_clk_pfdv2("apll_pfd1", "apll", base + 0x50c, 1);
- clks[IMX7ULP_CLK_APLL_PFD2] = imx_clk_pfdv2("apll_pfd2", "apll", base + 0x50c, 2);
- clks[IMX7ULP_CLK_APLL_PFD3] = imx_clk_pfdv2("apll_pfd3", "apll", base + 0x50c, 3);
+ clks[IMX7ULP_CLK_APLL_PFD0] = imx_clk_hw_pfdv2("apll_pfd0", "apll", base + 0x50c, 0);
+ clks[IMX7ULP_CLK_APLL_PFD1] = imx_clk_hw_pfdv2("apll_pfd1", "apll", base + 0x50c, 1);
+ clks[IMX7ULP_CLK_APLL_PFD2] = imx_clk_hw_pfdv2("apll_pfd2", "apll", base + 0x50c, 2);
+ clks[IMX7ULP_CLK_APLL_PFD3] = imx_clk_hw_pfdv2("apll_pfd3", "apll", base + 0x50c, 3);
/* SPLL PFDs */
- clks[IMX7ULP_CLK_SPLL_PFD0] = imx_clk_pfdv2("spll_pfd0", "spll", base + 0x60C, 0);
- clks[IMX7ULP_CLK_SPLL_PFD1] = imx_clk_pfdv2("spll_pfd1", "spll", base + 0x60C, 1);
- clks[IMX7ULP_CLK_SPLL_PFD2] = imx_clk_pfdv2("spll_pfd2", "spll", base + 0x60C, 2);
- clks[IMX7ULP_CLK_SPLL_PFD3] = imx_clk_pfdv2("spll_pfd3", "spll", base + 0x60C, 3);
+ clks[IMX7ULP_CLK_SPLL_PFD0] = imx_clk_hw_pfdv2("spll_pfd0", "spll", base + 0x60C, 0);
+ clks[IMX7ULP_CLK_SPLL_PFD1] = imx_clk_hw_pfdv2("spll_pfd1", "spll", base + 0x60C, 1);
+ clks[IMX7ULP_CLK_SPLL_PFD2] = imx_clk_hw_pfdv2("spll_pfd2", "spll", base + 0x60C, 2);
+ clks[IMX7ULP_CLK_SPLL_PFD3] = imx_clk_hw_pfdv2("spll_pfd3", "spll", base + 0x60C, 3);
/* PLL Mux */
clks[IMX7ULP_CLK_APLL_PFD_SEL] = imx_clk_hw_mux_flags("apll_pfd_sel", base + 0x508, 14, 2, apll_pfd_sels, ARRAY_SIZE(apll_pfd_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE);
diff --git a/drivers/clk/imx/clk-pfdv2.c b/drivers/clk/imx/clk-pfdv2.c
index a03bbed..de93ce7 100644
--- a/drivers/clk/imx/clk-pfdv2.c
+++ b/drivers/clk/imx/clk-pfdv2.c
@@ -166,7 +166,7 @@ static const struct clk_ops clk_pfdv2_ops = {
.is_enabled = clk_pfdv2_is_enabled,
};
-struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name,
+struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name,
void __iomem *reg, u8 idx)
{
struct clk_init_data init;
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index ee71aa9..c7285db 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -200,7 +200,7 @@ struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent,
struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name,
void __iomem *reg, u8 idx);
-struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name,
+struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name,
void __iomem *reg, u8 idx);
struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name,
--
2.7.4
next prev parent reply other threads:[~2019-12-11 9:26 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-11 9:25 [RESEND v2 00/11] clk: imx: Trivial cleanups for clk_hw based API Abel Vesa
2019-12-11 9:25 ` [RESEND v2 01/11] clk: imx: Add correct failure handling for clk based helpers Abel Vesa
2019-12-11 9:25 ` [RESEND v2 02/11] clk: imx: Rename the SCCG to SSCG Abel Vesa
2019-12-11 9:25 ` [RESEND v2 03/11] clk: imx: Replace all the clk based helpers with macros Abel Vesa
2019-12-11 9:25 ` [RESEND v2 04/11] clk: imx: pllv1: Switch to clk_hw based API Abel Vesa
2019-12-11 9:25 ` [RESEND v2 05/11] clk: imx: pllv2: " Abel Vesa
2019-12-11 9:25 ` [RESEND v2 06/11] clk: imx: imx7ulp composite: Rename to show is clk_hw based Abel Vesa
2019-12-11 9:25 ` [RESEND v2 07/11] clk: imx: Rename sccg and frac pll register to suggest clk_hw Abel Vesa
2019-12-11 9:25 ` [RESEND v2 08/11] clk: imx: Rename the imx_clk_pllv4 to imply it's clk_hw based Abel Vesa
2019-12-11 9:25 ` Abel Vesa [this message]
2019-12-11 9:25 ` [RESEND v2 10/11] clk: imx: Rename the imx_clk_divider_gate " Abel Vesa
2019-12-11 9:25 ` [RESEND v2 11/11] clk: imx7up: Rename the clks to hws Abel Vesa
2019-12-11 12:58 ` [RESEND v2 00/11] clk: imx: Trivial cleanups for clk_hw based API Shawn Guo
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