From: Kishon Vijay Abraham I <kishon@ti.com>
To: Rob Herring <robh+dt@kernel.org>,
Swapnil Kashinath Jakhade <sjakhade@cadence.com>,
Roger Quadros <rogerq@ti.com>, Jyri Sarha <jsarha@ti.com>
Cc: <devicetree@vger.kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Subject: [PATCH v5 13/14] dt-bindings: phy: Document WIZ (SERDES wrapper) bindings
Date: Thu, 2 Jan 2020 15:26:31 +0530 [thread overview]
Message-ID: <20200102095631.1165-1-kishon@ti.com> (raw)
In-Reply-To: <20191216095712.13266-14-kishon@ti.com>
Add DT binding documentation for WIZ (SERDES wrapper). WIZ is *NOT* a
PHY but a wrapper used to configure some of the input signals to the
SERDES. It is used with both Sierra(16G) and Torrent(10G) serdes.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
[jsarha@ti.com: Add separate compatible for Sierra(16G) and Torrent(10G)
SERDES]
Signed-off-by: Jyri Sarha <jsarha@ti.com>
---
Changes from v4:
*) Fixed the indentation as suggested by Rob v4
.../bindings/phy/ti,phy-j721e-wiz.yaml | 204 ++++++++++++++++++
1 file changed, 204 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
new file mode 100644
index 000000000000..e010ea46b88d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
@@ -0,0 +1,204 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: TI J721E WIZ (SERDES Wrapper)
+
+maintainers:
+ - Kishon Vijay Abraham I <kishon@ti.com>
+
+properties:
+ compatible:
+ enum:
+ - ti,j721e-wiz-16g
+ - ti,j721e-wiz-10g
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ maxItems: 3
+ description: clock-specifier to represent input to the WIZ
+
+ clock-names:
+ items:
+ - const: fck
+ - const: core_ref_clk
+ - const: ext_ref_clk
+
+ num-lanes:
+ minimum: 1
+ maximum: 4
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+ ranges: true
+
+ assigned-clocks:
+ maxItems: 2
+
+ assigned-clock-parents:
+ maxItems: 2
+
+patternProperties:
+ "^pll[0|1]-refclk$":
+ type: object
+ description: |
+ WIZ node should have subnodes for each of the PLLs present in
+ the SERDES.
+ properties:
+ clocks:
+ maxItems: 2
+ description: Phandle to clock nodes representing the two inputs to PLL.
+
+ "#clock-cells":
+ const: 0
+
+ assigned-clocks:
+ maxItems: 1
+
+ assigned-clock-parents:
+ maxItems: 1
+
+ required:
+ - clocks
+ - "#clock-cells"
+ - assigned-clocks
+ - assigned-clock-parents
+
+ "^cmn-refclk1?-dig-div$":
+ type: object
+ description:
+ WIZ node should have subnodes for each of the PMA common refclock
+ provided by the SERDES.
+ properties:
+ clocks:
+ maxItems: 1
+ description: Phandle to the clock node representing the input to the
+ divider clock.
+
+ "#clock-cells":
+ const: 0
+
+ required:
+ - clocks
+ - "#clock-cells"
+
+ "^refclk-dig$":
+ type: object
+ description: |
+ WIZ node should have subnode for refclk_dig to select the reference
+ clock source for the reference clock used in the PHY and PMA digital
+ logic.
+ properties:
+ clocks:
+ maxItems: 4
+ description: Phandle to four clock nodes representing the inputs to
+ refclk_dig
+
+ "#clock-cells":
+ const: 0
+
+ assigned-clocks:
+ maxItems: 1
+
+ assigned-clock-parents:
+ maxItems: 1
+
+ required:
+ - clocks
+ - "#clock-cells"
+ - assigned-clocks
+ - assigned-clock-parents
+
+ "^serdes@[0-9a-f]+$":
+ type: object
+ description: |
+ WIZ node should have '1' subnode for the SERDES. It could be either
+ Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the
+ bindings specified in
+ Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt
+ Torrent SERDES should follow the bindings specified in
+ Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
+
+required:
+ - compatible
+ - power-domains
+ - clocks
+ - clock-names
+ - num-lanes
+ - "#address-cells"
+ - "#size-cells"
+ - "#reset-cells"
+ - ranges
+
+examples:
+ - |
+ #include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+ wiz@5000000 {
+ compatible = "ti,j721e-wiz-16g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
+ assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
+ num-lanes = <2>;
+ #reset-cells = <1>;
+ ranges = <0x5000000 0x0 0x5000000 0x10000>;
+
+ pll0-refclk {
+ clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz1_pll0_refclk>;
+ assigned-clock-parents = <&k3_clks 293 13>;
+ };
+
+ pll1-refclk {
+ clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz1_pll1_refclk>;
+ assigned-clock-parents = <&k3_clks 293 0>;
+ };
+
+ cmn-refclk-dig-div {
+ clocks = <&wiz1_refclk_dig>;
+ #clock-cells = <0>;
+ };
+
+ cmn-refclk1-dig-div {
+ clocks = <&wiz1_pll1_refclk>;
+ #clock-cells = <0>;
+ };
+
+ refclk-dig {
+ clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_refclk_dig>;
+ assigned-clock-parents = <&k3_clks 292 11>;
+ };
+
+ serdes@5000000 {
+ compatible = "cdns,ti,sierra-phy-t0";
+ reg-names = "serdes";
+ reg = <0x5000000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = <&serdes_wiz0 0>;
+ reset-names = "sierra_reset";
+ clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ };
+ };
--
2.17.1
next prev parent reply other threads:[~2020-01-02 9:54 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-16 9:56 [PATCH v4 00/14] PHY: Add support for SERDES in TI's J721E SoC Kishon Vijay Abraham I
2019-12-16 9:56 ` [PATCH v4 01/14] dt-bindings: phy: Sierra: Add bindings for Sierra in TI's J721E Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 02/14] phy: cadence: Sierra: Make "phy_clk" and "sierra_apb" optional resources Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 03/14] phy: cadence: Sierra: Use "regmap" for read and write to Sierra registers Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 04/14] phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoC Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 05/14] phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_ops Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 06/14] phy: cadence: Sierra: Modify register macro names to be in sync with Sierra user guide Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 07/14] phy: cadence: Sierra: Configure both lane cdb and common cdb registers for external SSC Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 08/14] phy: cadence: Sierra: Get reset control "array" for each link Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 09/14] phy: cadence: Sierra: Check for PLL lock during PHY power on Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 10/14] phy: cadence: Sierra: Change MAX_LANES of Sierra to 16 Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 11/14] phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 12/14] phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove() Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 13/14] dt-bindings: phy: Document WIZ (SERDES wrapper) bindings Kishon Vijay Abraham I
2019-12-18 20:59 ` Rob Herring
2020-01-02 9:56 ` Kishon Vijay Abraham I [this message]
2020-01-03 22:34 ` [PATCH v5 " Rob Herring
2020-01-06 5:51 ` Kishon Vijay Abraham I
2020-01-13 17:59 ` Rob Herring
2020-01-14 8:06 ` Kishon Vijay Abraham I
2019-12-16 9:57 ` [PATCH v4 14/14] phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC Kishon Vijay Abraham I
2020-01-06 6:32 ` [PATCH v4 00/14] PHY: Add support for SERDES in TI's " Kishon Vijay Abraham I
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200102095631.1165-1-kishon@ti.com \
--to=kishon@ti.com \
--cc=devicetree@vger.kernel.org \
--cc=jsarha@ti.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=robh+dt@kernel.org \
--cc=rogerq@ti.com \
--cc=sjakhade@cadence.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).