From: Yash Shah <yash.shah@sifive.com>
To: robh+dt@kernel.org, mark.rutland@arm.com,
paul.walmsley@sifive.com, palmer@dabbelt.com
Cc: aou@eecs.berkeley.edu, bmeng.cn@gmail.com, green.wan@sifive.com,
allison@lohutok.net, alexios.zavras@intel.com,
gregkh@linuxfoundation.org, tglx@linutronix.de, bp@suse.de,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, sachin.ghadi@sifive.com,
Yash Shah <yash.shah@sifive.com>
Subject: [PATCH v2 1/2] riscv: dts: Add DT support for SiFive L2 cache controller
Date: Fri, 3 Jan 2020 09:43:20 +0530 [thread overview]
Message-ID: <1578024801-39039-2-git-send-email-yash.shah@sifive.com> (raw)
In-Reply-To: <1578024801-39039-1-git-send-email-yash.shah@sifive.com>
Add the L2 cache controller DT node in SiFive FU540 soc-specific DT file
Signed-off-by: Yash Shah <yash.shah@sifive.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 70a1891..a2e3d54 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -54,6 +54,7 @@
reg = <1>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -77,6 +78,7 @@
reg = <2>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -100,6 +102,7 @@
reg = <3>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -123,6 +126,7 @@
reg = <4>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -253,6 +257,17 @@
#pwm-cells = <3>;
status = "disabled";
};
+ l2cache: cache-controller@2010000 {
+ compatible = "sifive,fu540-c000-ccache", "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <1024>;
+ cache-size = <2097152>;
+ cache-unified;
+ interrupt-parent = <&plic0>;
+ interrupts = <1 2 3>;
+ reg = <0x0 0x2010000 0x0 0x1000>;
+ };
};
};
--
2.7.4
next prev parent reply other threads:[~2020-01-03 4:13 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-03 4:13 [PATCH v2 0/2] L2 ccache DT and cacheinfo support to read no. of L2 cache ways enabled Yash Shah
2020-01-03 4:13 ` Yash Shah [this message]
2020-01-04 0:57 ` [PATCH v2 1/2] riscv: dts: Add DT support for SiFive L2 cache controller Paul Walmsley
2020-01-03 4:13 ` [PATCH v2 2/2] riscv: cacheinfo: Add support to determine no. of L2 cache way enabled Yash Shah
2020-01-06 9:10 ` Anup Patel
2020-01-07 3:55 ` Yash Shah
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