From: Andre Przywara <andre.przywara@arm.com>
To: "David S . Miller" <davem@davemloft.net>,
Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>,
Robert Hancock <hancock@sedsystems.ca>,
netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 12/14] net: axienet: Autodetect 64-bit DMA capability
Date: Fri, 10 Jan 2020 11:54:13 +0000 [thread overview]
Message-ID: <20200110115415.75683-13-andre.przywara@arm.com> (raw)
In-Reply-To: <20200110115415.75683-1-andre.przywara@arm.com>
When newer revisions of the Axienet IP are configured for a 64-bit bus,
we *need* to write to the MSB part of the an address registers,
otherwise the IP won't recognise this as a DMA start condition.
This is even true when the actual DMA address comes from the lower 4 GB.
To autodetect this configuration, at probe time we write all 1's to such
an MSB register, and see if any bits stick. If this is configured for a
32-bit bus, those MSB registers are RES0, so reading back 0 indicates
that no MSB writes are necessary.
On the other hands reading anything other than 0 indicated the need to
write the MSB registers, so we set the respective flag.
For now this leaves the actual DMA mask at 32-bit, as we can't reliably
detect the actually wired number of address lines beyond 32.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/net/ethernet/xilinx/xilinx_axienet.h | 1 +
.../net/ethernet/xilinx/xilinx_axienet_main.c | 27 +++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h
index 4aea4c23d3bb..4feaaa02819c 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet.h
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h
@@ -161,6 +161,7 @@
#define XAE_FCC_OFFSET 0x0000040C /* Flow Control Configuration */
#define XAE_EMMC_OFFSET 0x00000410 /* EMAC mode configuration */
#define XAE_PHYC_OFFSET 0x00000414 /* RGMII/SGMII configuration */
+#define XAE_ID_OFFSET 0x000004F8 /* Identification register */
#define XAE_MDIO_MC_OFFSET 0x00000500 /* MII Management Config */
#define XAE_MDIO_MCR_OFFSET 0x00000504 /* MII Management Control */
#define XAE_MDIO_MWD_OFFSET 0x00000508 /* MII Management Write Data */
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index 133f088d797e..f7f593df0c11 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -151,6 +151,9 @@ static void axienet_dma_out_addr(struct axienet_local *lp, off_t reg,
dma_addr_t addr)
{
axienet_dma_out32(lp, reg, lower_32_bits(addr));
+
+ if (lp->features & XAE_FEATURE_DMA_64BIT)
+ axienet_dma_out32(lp, reg + 4, upper_32_bits(addr));
}
static void desc_set_phys_addr(struct axienet_local *lp, dma_addr_t addr,
@@ -1934,6 +1937,30 @@ static int axienet_probe(struct platform_device *pdev)
goto free_netdev;
}
+ /*
+ * Autodetect the need for 64-bit DMA pointers.
+ * When the IP is configured for a bus width bigger than 32 bits,
+ * writing the MSB registers is mandatory, even if they are all 0.
+ * We can detect this case by writing all 1's to one such register
+ * and see if that sticks: when the IP is configured for 32 bits
+ * only, those registers are RES0.
+ * Those MSB registers were introduced in IP v7.1, which we check first.
+ */
+ if ((axienet_ior(lp, XAE_ID_OFFSET) >> 24) >= 0x9) {
+ void __iomem *desc = lp->dma_regs + XAXIDMA_TX_CDESC_OFFSET + 4;
+
+ iowrite32(0x0, desc);
+ if (ioread32(desc) == 0) { /* sanity check */
+ iowrite32(0xffffffff, desc);
+ if (ioread32(desc) > 0) {
+ lp->features |= XAE_FEATURE_DMA_64BIT;
+ dev_info(&pdev->dev,
+ "autodetected 64-bit DMA range\n");
+ }
+ iowrite32(0x0, desc);
+ }
+ }
+
/* Check for Ethernet core IRQ (optional) */
if (lp->eth_irq <= 0)
dev_info(&pdev->dev, "Ethernet core IRQ not defined\n");
--
2.17.1
next prev parent reply other threads:[~2020-01-10 11:54 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-10 11:54 [PATCH 00/14] net: axienet: Error handling, SGMII and 64-bit DMA fixes Andre Przywara
2020-01-10 11:54 ` [PATCH 01/14] net: xilinx: temac: Relax Kconfig dependencies Andre Przywara
2020-01-10 14:19 ` Radhey Shyam Pandey
2020-01-10 11:54 ` [PATCH 02/14] net: axienet: Propagate failure of DMA descriptor setup Andre Przywara
2020-01-10 14:54 ` Radhey Shyam Pandey
2020-01-10 17:53 ` Radhey Shyam Pandey
2020-01-10 11:54 ` [PATCH 03/14] net: axienet: Fix DMA descriptor cleanup path Andre Przywara
2020-01-10 15:14 ` Radhey Shyam Pandey
2020-01-10 15:43 ` Andre Przywara
2020-01-10 17:05 ` Radhey Shyam Pandey
2020-01-16 18:03 ` Andre Przywara
2020-01-20 18:32 ` Radhey Shyam Pandey
2020-01-10 11:54 ` [PATCH 04/14] net: axienet: Improve DMA error handling Andre Przywara
2020-01-10 15:26 ` Radhey Shyam Pandey
2020-01-10 11:54 ` [PATCH 05/14] net: axienet: Factor out TX descriptor chain cleanup Andre Przywara
2020-01-10 18:04 ` Radhey Shyam Pandey
2020-01-10 11:54 ` [PATCH 06/14] net: axienet: Check for DMA mapping errors Andre Przywara
2020-01-13 5:54 ` Radhey Shyam Pandey
2020-01-10 11:54 ` [PATCH 07/14] net: axienet: Fix SGMII support Andre Przywara
2020-01-10 14:04 ` Andrew Lunn
2020-01-10 14:20 ` Andre Przywara
2020-01-10 14:26 ` Andrew Lunn
2020-01-10 15:04 ` Russell King - ARM Linux admin
2020-01-10 15:22 ` Russell King - ARM Linux admin
2020-01-10 17:04 ` Russell King - ARM Linux admin
2020-01-18 11:22 ` Russell King - ARM Linux admin
2020-01-20 14:50 ` Andre Przywara
2020-01-20 15:45 ` Russell King - ARM Linux admin
2020-01-27 17:04 ` Andre Przywara
2020-01-27 17:20 ` Radhey Shyam Pandey
2020-01-27 18:53 ` Russell King - ARM Linux admin
2020-04-22 1:45 ` Xilinx axienet 1000BaseX support (was: Re: [PATCH 07/14] net: axienet: Fix SGMII support) Robert Hancock
2020-04-22 7:51 ` Russell King - ARM Linux admin
2020-04-22 16:31 ` Xilinx axienet 1000BaseX support Robert Hancock
2020-04-28 21:59 ` Robert Hancock
2020-04-28 23:01 ` Russell King - ARM Linux admin
2020-04-28 23:51 ` Robert Hancock
2020-04-29 8:21 ` Russell King - ARM Linux admin
2020-01-10 14:58 ` [PATCH 07/14] net: axienet: Fix SGMII support Russell King - ARM Linux admin
2020-01-10 17:32 ` Andre Przywara
2020-01-10 18:05 ` Russell King - ARM Linux admin
2020-01-10 19:33 ` Andrew Lunn
2020-01-10 11:54 ` [PATCH 08/14] net: axienet: Drop MDIO interrupt registers from ethtools dump Andre Przywara
2020-01-13 6:02 ` Radhey Shyam Pandey
2020-01-10 11:54 ` [PATCH 09/14] net: axienet: Add mii-tool support Andre Przywara
2020-01-13 6:12 ` Radhey Shyam Pandey
2020-03-12 11:41 ` Andre Przywara
2020-01-10 11:54 ` [PATCH 10/14] net: axienet: Wrap DMA pointer writes to prepare for 64 bit Andre Przywara
2020-01-10 11:54 ` [PATCH 11/14] net: axienet: Upgrade descriptors to hold 64-bit addresses Andre Przywara
2020-01-14 16:35 ` Radhey Shyam Pandey
2020-01-14 17:29 ` Andre Przywara
2020-01-10 11:54 ` Andre Przywara [this message]
2020-01-10 14:08 ` [PATCH 12/14] net: axienet: Autodetect 64-bit DMA capability Andrew Lunn
2020-01-10 14:13 ` Andre Przywara
2020-01-10 14:22 ` Andrew Lunn
2020-01-10 15:08 ` Andre Przywara
2020-01-10 15:22 ` Andrew Lunn
2020-01-14 17:03 ` Radhey Shyam Pandey
2020-01-14 17:41 ` Andre Przywara
2020-01-15 6:02 ` Radhey Shyam Pandey
2020-01-10 11:54 ` [PATCH 13/14] net: axienet: Allow DMA to beyond 4GB Andre Przywara
2020-01-10 11:54 ` [PATCH 14/14] net: axienet: Update devicetree binding documentation Andre Przywara
2020-01-21 21:51 ` Rob Herring
2020-01-24 16:29 ` Andre Przywara
2020-01-27 9:28 ` Radhey Shyam Pandey
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