From: Chunyan Zhang <zhang.lyra@gmail.com>
To: Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Orson Zhai <orsonzhai@gmail.com>,
Baolin Wang <baolin.wang7@gmail.com>,
Chunyan Zhang <zhang.lyra@gmail.com>,
Chunyan Zhang <chunyan.zhang@unisoc.com>
Subject: [PATCH v4 3/7] dt-bindings: clk: sprd: add bindings for sc9863a clock controller
Date: Mon, 17 Feb 2020 11:23:17 +0800 [thread overview]
Message-ID: <20200217032321.15164-4-zhang.lyra@gmail.com> (raw)
In-Reply-To: <20200217032321.15164-1-zhang.lyra@gmail.com>
From: Chunyan Zhang <chunyan.zhang@unisoc.com>
add a new bindings to describe sc9863a clock compatible string.
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
---
.../bindings/clock/sprd,sc9863a-clk.yaml | 103 ++++++++++++++++++
1 file changed, 103 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml
diff --git a/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml
new file mode 100644
index 000000000000..e19577a6142a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2019 Unisoc Inc.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: SC9863A Clock Control Unit Device Tree Bindings
+
+maintainers:
+ - Orson Zhai <orsonzhai@gmail.com>
+ - Baolin Wang <baolin.wang7@gmail.com>
+ - Chunyan Zhang <zhang.lyra@gmail.com>
+
+properties:
+ "#clock-cells":
+ const: 1
+
+ compatible :
+ enum:
+ - sprd,sc9863a-ap-clk
+ - sprd,sc9863a-aon-clk
+ - sprd,sc9863a-apahb-gate
+ - sprd,sc9863a-pmu-gate
+ - sprd,sc9863a-aonapb-gate
+ - sprd,sc9863a-pll
+ - sprd,sc9863a-mpll
+ - sprd,sc9863a-rpll
+ - sprd,sc9863a-dpll
+ - sprd,sc9863a-mm-gate
+ - sprd,sc9863a-apapb-gate
+
+ clocks:
+ maxItems: 4
+ description: |
+ The input parent clock(s) phandle for this clock, only list fixed
+ clocks which are declared in devicetree.
+
+ clock-names:
+ maxItems: 4
+ description: |
+ Clock name strings used for driver to reference.
+ items:
+ - const: ext-26m
+ - const: ext-32k
+ - const: ext-4m
+ - const: rco-100m
+
+ reg:
+ description: |
+ Contain the registers base address and length.
+
+required:
+ - compatible
+ - '#clock-cells'
+
+if:
+ properties:
+ compatible:
+ enum:
+ - sprd,sc9863a-ap-clk
+ - sprd,sc9863a-aon-clk
+then:
+ required:
+ - reg
+
+else:
+ description: |
+ Other SC9863a clock nodes should be the child of a syscon node with
+ the required property:
+
+ - compatible: Should be the following:
+ "sprd,sc9863a-glbregs", "syscon", "simple-mfd"
+
+ The 'reg' property is also required if there is a sub range of
+ registers for the clocks that are contiguous.
+
+examples:
+ - |
+ ap_clk: clock-controller@21500000 {
+ compatible = "sprd,sc9863a-ap-clk";
+ reg = <0 0x21500000 0 0x1000>;
+ clocks = <&ext_26m>, <&ext_32k>;
+ clock-names = "ext-26m", "ext-32k";
+ #clock-cells = <1>;
+ };
+
+ - |
+ ap_ahb_regs: syscon@20e00000 {
+ compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd";
+ reg = <0 0x20e00000 0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x20e00000 0x4000>;
+
+ apahb_gate: apahb-gate@0 {
+ compatible = "sprd,sc9863a-apahb-gate";
+ reg = <0x0 0x1020>;
+ #clock-cells = <1>;
+ };
+ };
+
+...
--
2.20.1
next prev parent reply other threads:[~2020-02-17 3:23 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-17 3:23 [PATCH v4 0/7] Add clocks for Unisoc's SC9863A Chunyan Zhang
2020-02-17 3:23 ` [PATCH v4 1/7] clk: sprd: add gate for pll clocks Chunyan Zhang
2020-02-17 3:23 ` [PATCH v4 2/7] dt-bindings: clk: sprd: rename the common file name sprd.txt to SoC specific Chunyan Zhang
2020-02-17 3:23 ` Chunyan Zhang [this message]
2020-02-18 23:00 ` [PATCH v4 3/7] dt-bindings: clk: sprd: add bindings for sc9863a clock controller Rob Herring
2020-02-17 3:23 ` [PATCH v4 4/7] clk: sprd: Add dt-bindings include file for SC9863A Chunyan Zhang
2020-02-17 3:23 ` [PATCH v4 5/7] clk: sprd: Add macros for referencing parents without strings Chunyan Zhang
2020-02-17 3:23 ` [PATCH v4 6/7] clk: sprd: support to get regmap from parent node Chunyan Zhang
2020-02-17 3:23 ` [PATCH v4 7/7] clk: sprd: add clocks support for SC9863A Chunyan Zhang
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