From: Kalyani Akula <kalyani.akula@xilinx.com>
To: herbert@gondor.apana.org.au, davem@davemloft.net,
monstr@seznam.cz, linux-crypto@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: Kalyani Akula <kalyania@xilinx.com>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, git-dev@xilinx.com,
Mohan Marutirao Dhanawade <mohan.dhanawade@xilinx.com>,
Sarat Chand Savitala <saratcha@xilinx.com>,
Harsh Jain <harshj@xilinx.com>, Michal Simek <michals@xilinx.com>,
Kalyani Akula <kalyani.akula@xilinx.com>
Subject: [PATCH V7 1/4] firmware: xilinx: Add ZynqMP aes API for AES functionality
Date: Mon, 17 Feb 2020 15:56:41 +0530 [thread overview]
Message-ID: <1581935204-25673-2-git-send-email-kalyani.akula@xilinx.com> (raw)
In-Reply-To: <1581935204-25673-1-git-send-email-kalyani.akula@xilinx.com>
Add ZynqMP firmware AES API to perform encryption/decryption of given data.
Signed-off-by: Kalyani Akula <kalyani.akula@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
---
V5 Changes:
- Moved firmware: xilinx: Add ZynqMP aes API for AES patch from 3/4 to 1/4
- This patch (1/4) is based on below commit id because of possible merge conflict
commit 461011b1e1ab ("drivers: firmware: xilinx: Add support for feature check")
- Added newlines in between at the start and end of zynqmp_pm_aes_engine function
drivers/firmware/xilinx/zynqmp.c | 25 +++++++++++++++++++++++++
include/linux/firmware/xlnx-zynqmp.h | 2 ++
2 files changed, 27 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index ecc339d..1dea880 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -707,6 +707,30 @@ static int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
qos, ack, NULL);
}
+/**
+ * zynqmp_pm_aes - Access AES hardware to encrypt/decrypt the data using
+ * AES-GCM core.
+ * @address: Address of the AesParams structure.
+ * @out: Returned output value
+ *
+ * Return: Returns status, either success or error code.
+ */
+static int zynqmp_pm_aes_engine(const u64 address, u32 *out)
+{
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ int ret;
+
+ if (!out)
+ return -EINVAL;
+
+ ret = zynqmp_pm_invoke_fn(PM_SECURE_AES, upper_32_bits(address),
+ lower_32_bits(address),
+ 0, 0, ret_payload);
+ *out = ret_payload[1];
+
+ return ret;
+}
+
static const struct zynqmp_eemi_ops eemi_ops = {
.get_api_version = zynqmp_pm_get_api_version,
.get_chipid = zynqmp_pm_get_chipid,
@@ -730,6 +754,7 @@ static int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
.set_requirement = zynqmp_pm_set_requirement,
.fpga_load = zynqmp_pm_fpga_load,
.fpga_get_status = zynqmp_pm_fpga_get_status,
+ .aes = zynqmp_pm_aes_engine,
};
/**
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 2cd12eb..8acace4 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -82,6 +82,7 @@ enum pm_api_id {
PM_CLOCK_GETRATE,
PM_CLOCK_SETPARENT,
PM_CLOCK_GETPARENT,
+ PM_SECURE_AES = 47,
PM_FEATURE_CHECK = 63,
PM_API_MAX,
};
@@ -315,6 +316,7 @@ struct zynqmp_eemi_ops {
const u32 capabilities,
const u32 qos,
const enum zynqmp_pm_request_ack ack);
+ int (*aes)(const u64 address, u32 *out);
};
int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
--
1.9.5
next prev parent reply other threads:[~2020-02-17 10:27 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-17 10:26 [PATCH V7 0/4] Add Xilinx's ZynqMP AES-GCM driver support Kalyani Akula
2020-02-17 10:26 ` Kalyani Akula [this message]
2020-02-17 10:26 ` [PATCH V7 2/4] dt-bindings: crypto: Add bindings for ZynqMP AES-GCM driver Kalyani Akula
2020-02-17 10:26 ` [PATCH V7 3/4] crypto: Add Xilinx AES driver Kalyani Akula
2020-02-17 10:26 ` [PATCH V7 4/4] arm64: zynqmp: Add Xilinx AES node Kalyani Akula
2020-02-28 7:11 ` Michal Simek
2020-02-28 0:50 ` [PATCH V7 0/4] Add Xilinx's ZynqMP AES-GCM driver support Herbert Xu
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