From: Atish Patra <atish.patra@wdc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atish.patra@wdc.com>,
Anup Patel <anup@brainfault.org>,
Palmer Dabbelt <palmerdabbelt@google.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexios Zavras <alexios.zavras@intel.com>,
Borislav Petkov <bp@suse.de>,
Daniel Jordan <daniel.m.jordan@oracle.com>,
"Eric W. Biederman" <ebiederm@xmission.com>,
Gary Guo <gary@garyguo.net>,
Geert Uytterhoeven <geert@linux-m68k.org>,
Greentime Hu <greentime.hu@sifive.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Heiko Carstens <heiko.carstens@de.ibm.com>,
Jason Cooper <jason@lakedaemon.net>,
Kate Stewart <kstewart@linuxfoundation.org>,
Kees Cook <keescook@chromium.org>,
linux-riscv@lists.infradead.org,
Madhavan Srinivasan <maddy@linux.vnet.ibm.com>,
Mao Han <han_mao@c-sky.com>, Marc Zyngier <maz@kernel.org>,
Michael Kelley <mikelley@microsoft.com>,
Mike Rapoport <rppt@linux.ibm.com>,
Nick Hu <nickhu@andestech.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
"Rafael J. Wysocki" <rafael.j.wysocki@intel.com>,
Steven Price <steven.price@arm.com>,
Sudeep Holla <sudeep.holla@arm.com>,
Thomas Gleixner <tglx@linutronix.de>,
Vincent Chen <vincent.chen@sifive.com>,
Zong Li <zong.li@sifive.com>
Subject: [PATCH v10 03/12] RISC-V: Add SBI v0.2 extension definitions
Date: Wed, 26 Feb 2020 14:02:04 -0800 [thread overview]
Message-ID: <20200226220213.27423-4-atish.patra@wdc.com> (raw)
In-Reply-To: <20200226220213.27423-1-atish.patra@wdc.com>
Few v0.1 SBI calls are being replaced by new SBI calls that follows
v0.2 calling convention.
This patch just defines these new extensions.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
arch/riscv/include/asm/sbi.h | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 5a3937792b8f..1c4bdcc3b817 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -21,6 +21,9 @@ enum sbi_ext_id {
SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
SBI_EXT_0_1_SHUTDOWN = 0x8,
SBI_EXT_BASE = 0x10,
+ SBI_EXT_TIME = 0x54494D45,
+ SBI_EXT_IPI = 0x735049,
+ SBI_EXT_RFENCE = 0x52464E43,
};
enum sbi_ext_base_fid {
@@ -33,6 +36,24 @@ enum sbi_ext_base_fid {
SBI_EXT_BASE_GET_MIMPID,
};
+enum sbi_ext_time_fid {
+ SBI_EXT_TIME_SET_TIMER = 0,
+};
+
+enum sbi_ext_ipi_fid {
+ SBI_EXT_IPI_SEND_IPI = 0,
+};
+
+enum sbi_ext_rfence_fid {
+ SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
+ SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
+ SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
+};
+
#define SBI_SPEC_VERSION_DEFAULT 0x1
#define SBI_SPEC_VERSION_MAJOR_SHIFT 24
#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
--
2.25.0
next prev parent reply other threads:[~2020-02-26 22:02 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-26 22:02 [PATCH v10 00/12] Add support for SBI v0.2 and CPU hotplug Atish Patra
2020-02-26 22:02 ` [PATCH v10 01/12] RISC-V: Mark existing SBI as 0.1 SBI Atish Patra
2020-03-06 5:43 ` Bin Meng
2020-02-26 22:02 ` [PATCH v10 02/12] RISC-V: Add basic support for SBI v0.2 Atish Patra
2020-03-06 5:34 ` Bin Meng
2020-02-26 22:02 ` Atish Patra [this message]
2020-02-26 22:02 ` [PATCH v10 04/12] RISC-V: Introduce a new config for SBI v0.1 Atish Patra
2020-02-26 22:02 ` [PATCH v10 05/12] RISC-V: Implement new SBI v0.2 extensions Atish Patra
2020-02-26 22:02 ` [PATCH v10 06/12] RISC-V: Move relocate and few other functions out of __init Atish Patra
2020-02-26 22:02 ` [PATCH v10 07/12] RISC-V: Add cpu_ops and modify default booting method Atish Patra
2020-02-26 22:02 ` [PATCH v10 08/12] RISC-V: Export SBI error to linux error mapping function Atish Patra
2020-02-26 22:02 ` [PATCH v10 09/12] RISC-V: Add SBI HSM extension definitions Atish Patra
2020-02-26 22:02 ` [PATCH v10 10/12] RISC-V: Add supported for ordered booting method using HSM Atish Patra
2020-02-26 22:02 ` [PATCH v10 11/12] RISC-V: Support cpu hotplug Atish Patra
2020-02-26 22:02 ` [PATCH v10 12/12] irqchip/sifive-plic: Initialize the plic handler when cpu comes online Atish Patra
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