From: Atish Patra <atish.patra@wdc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atish.patra@wdc.com>,
Anup Patel <anup@brainfault.org>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexios Zavras <alexios.zavras@intel.com>,
Borislav Petkov <bp@suse.de>,
Daniel Jordan <daniel.m.jordan@oracle.com>,
"Eric W. Biederman" <ebiederm@xmission.com>,
Gary Guo <gary@garyguo.net>,
Geert Uytterhoeven <geert@linux-m68k.org>,
Greentime Hu <greentime.hu@sifive.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Heiko Carstens <heiko.carstens@de.ibm.com>,
Jason Cooper <jason@lakedaemon.net>,
Kate Stewart <kstewart@linuxfoundation.org>,
Kees Cook <keescook@chromium.org>,
linux-riscv@lists.infradead.org,
Madhavan Srinivasan <maddy@linux.vnet.ibm.com>,
Mao Han <han_mao@c-sky.com>, Marc Zyngier <maz@kernel.org>,
Michael Kelley <mikelley@microsoft.com>,
Mike Rapoport <rppt@linux.ibm.com>,
Nick Hu <nickhu@andestech.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
"Rafael J. Wysocki" <rafael.j.wysocki@intel.com>,
Steven Price <steven.price@arm.com>,
Sudeep Holla <sudeep.holla@arm.com>,
Thomas Gleixner <tglx@linutronix.de>,
Vincent Chen <vincent.chen@sifive.com>,
Zong Li <zong.li@sifive.com>
Subject: [PATCH v10 10/12] RISC-V: Add supported for ordered booting method using HSM
Date: Wed, 26 Feb 2020 14:02:11 -0800 [thread overview]
Message-ID: <20200226220213.27423-11-atish.patra@wdc.com> (raw)
In-Reply-To: <20200226220213.27423-1-atish.patra@wdc.com>
Currently, all harts have to jump Linux in RISC-V. This complicates the
multi-stage boot process as every transient stage also has to ensure all
harts enter to that stage and jump to Linux afterwards. It also obstructs
a clean Kexec implementation.
SBI HSM extension provides alternate solutions where only a single hart
need to boot and enter Linux. The booting hart can bring up secondary
harts one by one afterwards.
Add SBI HSM based cpu_ops that implements an ordered booting method in
RISC-V. This change is also backward compatible with older firmware not
implementing HSM extension. If a latest kernel is used with older
firmware, it will continue to use the default spinning booting method.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
arch/riscv/kernel/Makefile | 3 ++
arch/riscv/kernel/cpu_ops.c | 10 +++-
arch/riscv/kernel/cpu_ops_sbi.c | 81 +++++++++++++++++++++++++++++++++
arch/riscv/kernel/head.S | 26 +++++++++++
arch/riscv/kernel/smpboot.c | 2 +-
arch/riscv/kernel/traps.c | 2 +-
6 files changed, 121 insertions(+), 3 deletions(-)
create mode 100644 arch/riscv/kernel/cpu_ops_sbi.c
diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
index f81a6ff88005..a0be34b96846 100644
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@ -44,5 +44,8 @@ obj-$(CONFIG_PERF_EVENTS) += perf_event.o
obj-$(CONFIG_PERF_EVENTS) += perf_callchain.o
obj-$(CONFIG_HAVE_PERF_REGS) += perf_regs.o
obj-$(CONFIG_RISCV_SBI) += sbi.o
+ifeq ($(CONFIG_RISCV_SBI), y)
+obj-$(CONFIG_SMP) += cpu_ops_sbi.o
+endif
clean:
diff --git a/arch/riscv/kernel/cpu_ops.c b/arch/riscv/kernel/cpu_ops.c
index e950ae5bee9c..afa90f711a2b 100644
--- a/arch/riscv/kernel/cpu_ops.c
+++ b/arch/riscv/kernel/cpu_ops.c
@@ -18,6 +18,7 @@ const struct cpu_operations *cpu_ops[NR_CPUS] __ro_after_init;
void *__cpu_up_stack_pointer[NR_CPUS];
void *__cpu_up_task_pointer[NR_CPUS];
+extern const struct cpu_operations cpu_ops_sbi;
extern const struct cpu_operations cpu_ops_spinwait;
void cpu_update_secondary_bootdata(unsigned int cpuid,
@@ -34,5 +35,12 @@ void cpu_update_secondary_bootdata(unsigned int cpuid,
void __init cpu_set_ops(int cpuid)
{
- cpu_ops[cpuid] = &cpu_ops_spinwait;
+#if IS_ENABLED(CONFIG_RISCV_SBI)
+ if (sbi_probe_extension(SBI_EXT_HSM) > 0) {
+ if (!cpuid)
+ pr_info("SBI v0.2 HSM extension detected\n");
+ cpu_ops[cpuid] = &cpu_ops_sbi;
+ } else
+#endif
+ cpu_ops[cpuid] = &cpu_ops_spinwait;
}
diff --git a/arch/riscv/kernel/cpu_ops_sbi.c b/arch/riscv/kernel/cpu_ops_sbi.c
new file mode 100644
index 000000000000..70d02dfe0ab8
--- /dev/null
+++ b/arch/riscv/kernel/cpu_ops_sbi.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * HSM extension and cpu_ops implementation.
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ */
+
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <asm/cpu_ops.h>
+#include <asm/sbi.h>
+#include <asm/smp.h>
+
+extern char secondary_start_sbi[];
+const struct cpu_operations cpu_ops_sbi;
+
+static int sbi_hsm_hart_start(unsigned long hartid, unsigned long saddr,
+ unsigned long priv)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_HSM, SBI_EXT_HSM_HART_START,
+ hartid, saddr, priv, 0, 0, 0);
+ if (ret.error)
+ return sbi_err_map_linux_errno(ret.error);
+ else
+ return 0;
+}
+
+#ifdef CONFIG_HOTPLUG_CPU
+static int sbi_hsm_hart_stop(void)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_HSM, SBI_EXT_HSM_HART_STOP, 0, 0, 0, 0, 0, 0);
+
+ if (ret.error)
+ return sbi_err_map_linux_errno(ret.error);
+ else
+ return 0;
+}
+
+static int sbi_hsm_hart_get_status(unsigned long hartid)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_HSM, SBI_EXT_HSM_HART_STATUS,
+ hartid, 0, 0, 0, 0, 0);
+ if (ret.error)
+ return sbi_err_map_linux_errno(ret.error);
+ else
+ return ret.value;
+}
+#endif
+
+static int sbi_cpu_start(unsigned int cpuid, struct task_struct *tidle)
+{
+ int rc;
+ unsigned long boot_addr = __pa_symbol(secondary_start_sbi);
+ int hartid = cpuid_to_hartid_map(cpuid);
+
+ cpu_update_secondary_bootdata(cpuid, tidle);
+ rc = sbi_hsm_hart_start(hartid, boot_addr, 0);
+
+ return rc;
+}
+
+static int sbi_cpu_prepare(unsigned int cpuid)
+{
+ if (!cpu_ops_sbi.cpu_start) {
+ pr_err("cpu start method not defined for CPU [%d]\n", cpuid);
+ return -ENODEV;
+ }
+ return 0;
+}
+
+const struct cpu_operations cpu_ops_sbi = {
+ .name = "sbi",
+ .cpu_prepare = sbi_cpu_prepare,
+ .cpu_start = sbi_cpu_start,
+};
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index b85376d84098..ac5b0e0a02f6 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -99,11 +99,37 @@ relocate:
ret
#endif /* CONFIG_MMU */
#ifdef CONFIG_SMP
+ .global secondary_start_sbi
+secondary_start_sbi:
+ /* Mask all interrupts */
+ csrw CSR_IE, zero
+ csrw CSR_IP, zero
+
+ /* Load the global pointer */
+ .option push
+ .option norelax
+ la gp, __global_pointer$
+ .option pop
+
+ /*
+ * Disable FPU to detect illegal usage of
+ * floating point in kernel space
+ */
+ li t0, SR_FS
+ csrc CSR_STATUS, t0
+
/* Set trap vector to spin forever to help debug */
la a3, .Lsecondary_park
csrw CSR_TVEC, a3
slli a3, a0, LGREG
+ la a4, __cpu_up_stack_pointer
+ la a5, __cpu_up_task_pointer
+ add a4, a3, a4
+ add a5, a3, a5
+ REG_L sp, (a4)
+ REG_L tp, (a5)
+
.global secondary_start_common
secondary_start_common:
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index e89396a2a1af..4e9922790f6e 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -143,7 +143,7 @@ void __init smp_cpus_done(unsigned int max_cpus)
/*
* C entry point for a secondary processor.
*/
-asmlinkage __visible void __init smp_callin(void)
+asmlinkage __visible void smp_callin(void)
{
struct mm_struct *mm = &init_mm;
diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
index ffb3d94bf0cc..8e13ad45ccaa 100644
--- a/arch/riscv/kernel/traps.c
+++ b/arch/riscv/kernel/traps.c
@@ -147,7 +147,7 @@ int is_valid_bugaddr(unsigned long pc)
}
#endif /* CONFIG_GENERIC_BUG */
-void __init trap_init(void)
+void trap_init(void)
{
/*
* Set sup0 scratch register to 0, indicating to exception vector
--
2.25.0
next prev parent reply other threads:[~2020-02-26 22:02 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-26 22:02 [PATCH v10 00/12] Add support for SBI v0.2 and CPU hotplug Atish Patra
2020-02-26 22:02 ` [PATCH v10 01/12] RISC-V: Mark existing SBI as 0.1 SBI Atish Patra
2020-03-06 5:43 ` Bin Meng
2020-02-26 22:02 ` [PATCH v10 02/12] RISC-V: Add basic support for SBI v0.2 Atish Patra
2020-03-06 5:34 ` Bin Meng
2020-02-26 22:02 ` [PATCH v10 03/12] RISC-V: Add SBI v0.2 extension definitions Atish Patra
2020-02-26 22:02 ` [PATCH v10 04/12] RISC-V: Introduce a new config for SBI v0.1 Atish Patra
2020-02-26 22:02 ` [PATCH v10 05/12] RISC-V: Implement new SBI v0.2 extensions Atish Patra
2020-02-26 22:02 ` [PATCH v10 06/12] RISC-V: Move relocate and few other functions out of __init Atish Patra
2020-02-26 22:02 ` [PATCH v10 07/12] RISC-V: Add cpu_ops and modify default booting method Atish Patra
2020-02-26 22:02 ` [PATCH v10 08/12] RISC-V: Export SBI error to linux error mapping function Atish Patra
2020-02-26 22:02 ` [PATCH v10 09/12] RISC-V: Add SBI HSM extension definitions Atish Patra
2020-02-26 22:02 ` Atish Patra [this message]
2020-02-26 22:02 ` [PATCH v10 11/12] RISC-V: Support cpu hotplug Atish Patra
2020-02-26 22:02 ` [PATCH v10 12/12] irqchip/sifive-plic: Initialize the plic handler when cpu comes online Atish Patra
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