From: Ravi Bangoria <ravi.bangoria@linux.ibm.com>
To: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
Cc: eranian@google.com, peterz@infradead.org, mpe@ellerman.id.au,
paulus@samba.org, mingo@redhat.com, acme@kernel.org,
mark.rutland@arm.com, alexander.shishkin@linux.intel.com,
jolsa@redhat.com, namhyung@kernel.org, adrian.hunter@intel.com,
ak@linux.intel.com, kan.liang@linux.intel.com,
alexey.budankov@linux.intel.com, yao.jin@linux.intel.com,
robert.richter@amd.com, kim.phillips@amd.com,
maddy@linux.ibm.com, ravi.bangoria@linux.ibm.com
Subject: [RFC 01/11] powerpc/perf: Simplify ISA207_SIER macros
Date: Mon, 2 Mar 2020 10:53:45 +0530 [thread overview]
Message-ID: <20200302052355.36365-2-ravi.bangoria@linux.ibm.com> (raw)
In-Reply-To: <20200302052355.36365-1-ravi.bangoria@linux.ibm.com>
Instead of having separate macros for MASK and SHIFT, and using
them to derive the bits, let's have simple macro to do the job.
Also, remove ISA207_ prefix because some of the SIER bits which
are extracted with these macros are not defined in ISA, example
DATA_SRC bits.
Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com>
---
arch/powerpc/perf/isa207-common.c | 8 ++++----
arch/powerpc/perf/isa207-common.h | 11 +++--------
2 files changed, 7 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c
index 4c86da5eb28a..07026bbd292b 100644
--- a/arch/powerpc/perf/isa207-common.c
+++ b/arch/powerpc/perf/isa207-common.c
@@ -215,10 +215,10 @@ void isa207_get_mem_data_src(union perf_mem_data_src *dsrc, u32 flags,
}
sier = mfspr(SPRN_SIER);
- val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT;
+ val = SIER_TYPE(sier);
if (val == 1 || val == 2) {
- idx = (sier & ISA207_SIER_LDST_MASK) >> ISA207_SIER_LDST_SHIFT;
- sub_idx = (sier & ISA207_SIER_DATA_SRC_MASK) >> ISA207_SIER_DATA_SRC_SHIFT;
+ idx = SIER_LDST(sier);
+ sub_idx = SIER_DATA_SRC(sier);
dsrc->val = isa207_find_source(idx, sub_idx);
dsrc->val |= (val == 1) ? P(OP, LOAD) : P(OP, STORE);
@@ -231,7 +231,7 @@ void isa207_get_mem_weight(u64 *weight)
u64 exp = MMCRA_THR_CTR_EXP(mmcra);
u64 mantissa = MMCRA_THR_CTR_MANT(mmcra);
u64 sier = mfspr(SPRN_SIER);
- u64 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT;
+ u64 val = SIER_TYPE(sier);
if (val == 0 || val == 7)
*weight = 0;
diff --git a/arch/powerpc/perf/isa207-common.h b/arch/powerpc/perf/isa207-common.h
index 63fd4f3f6013..7027eb9f3e40 100644
--- a/arch/powerpc/perf/isa207-common.h
+++ b/arch/powerpc/perf/isa207-common.h
@@ -202,14 +202,9 @@
#define MAX_ALT 2
#define MAX_PMU_COUNTERS 6
-#define ISA207_SIER_TYPE_SHIFT 15
-#define ISA207_SIER_TYPE_MASK (0x7ull << ISA207_SIER_TYPE_SHIFT)
-
-#define ISA207_SIER_LDST_SHIFT 1
-#define ISA207_SIER_LDST_MASK (0x7ull << ISA207_SIER_LDST_SHIFT)
-
-#define ISA207_SIER_DATA_SRC_SHIFT 53
-#define ISA207_SIER_DATA_SRC_MASK (0x7ull << ISA207_SIER_DATA_SRC_SHIFT)
+#define SIER_DATA_SRC(sier) (((sier) >> (63 - 10)) & 0x7ull)
+#define SIER_TYPE(sier) (((sier) >> (63 - 48)) & 0x7ull)
+#define SIER_LDST(sier) (((sier) >> (63 - 62)) & 0x7ull)
#define P(a, b) PERF_MEM_S(a, b)
#define PH(a, b) (P(LVL, HIT) | P(a, b))
--
2.21.1
next prev parent reply other threads:[~2020-03-02 5:24 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-02 5:23 [RFC 00/11] perf: Enhancing perf to export processor hazard information Ravi Bangoria
2020-03-02 5:23 ` Ravi Bangoria [this message]
2020-03-02 5:23 ` [RFC 02/11] perf/core: Data structure to present hazard data Ravi Bangoria
2020-03-02 9:55 ` Peter Zijlstra
2020-03-02 14:23 ` maddy
2020-03-02 14:48 ` Mark Rutland
2020-03-03 14:32 ` Ravi Bangoria
2020-03-02 14:54 ` Mark Rutland
2020-03-03 14:31 ` Ravi Bangoria
2020-03-02 5:23 ` [RFC 03/11] powerpc/perf: Arch specific definitions for pipeline Ravi Bangoria
2020-03-02 5:23 ` [RFC 04/11] powerpc/perf: Arch support to expose Hazard data Ravi Bangoria
2020-03-02 5:23 ` [RFC 05/11] perf tools: Enable record and script to record and show hazard data Ravi Bangoria
2020-03-02 5:23 ` [RFC 06/11] perf hists: Make a room for hazard info in struct hist_entry Ravi Bangoria
2020-03-02 5:23 ` [RFC 07/11] perf hazard: Functions to convert generic hazard data to arch specific string Ravi Bangoria
2020-03-02 5:23 ` [RFC 08/11] perf report: Enable hazard mode Ravi Bangoria
2020-03-02 5:23 ` [RFC 09/11] perf annotate: Introduce type for annotation_line Ravi Bangoria
2020-03-02 5:23 ` [RFC 10/11] perf annotate: Preparation for hazard Ravi Bangoria
2020-03-02 5:23 ` [RFC 11/11] perf annotate: Show hazard data in tui mode Ravi Bangoria
2020-03-02 10:13 ` [RFC 00/11] perf: Enhancing perf to export processor hazard information Peter Zijlstra
2020-03-02 20:21 ` Stephane Eranian
2020-03-02 22:25 ` Kim Phillips
2020-03-05 4:46 ` Ravi Bangoria
2020-03-05 22:06 ` Kim Phillips
2020-03-11 16:00 ` Ravi Bangoria
2020-03-12 22:38 ` Kim Phillips
2020-03-17 6:50 ` maddy
2020-03-18 17:35 ` Kim Phillips
2020-03-19 11:22 ` Michael Ellerman
2020-03-26 10:19 ` maddy
2020-03-26 19:48 ` Kim Phillips
2020-04-20 7:09 ` Madhavan Srinivasan
2020-04-27 7:18 ` Madhavan Srinivasan
2020-03-05 4:28 ` maddy
2020-03-03 1:33 ` Andi Kleen
2020-03-05 5:06 ` Ravi Bangoria
2020-03-02 21:08 ` Paul Clarke
2020-03-05 5:06 ` Ravi Bangoria
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