From: Ravi Bangoria <ravi.bangoria@linux.ibm.com>
To: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
Cc: eranian@google.com, peterz@infradead.org, mpe@ellerman.id.au,
paulus@samba.org, mingo@redhat.com, acme@kernel.org,
mark.rutland@arm.com, alexander.shishkin@linux.intel.com,
jolsa@redhat.com, namhyung@kernel.org, adrian.hunter@intel.com,
ak@linux.intel.com, kan.liang@linux.intel.com,
alexey.budankov@linux.intel.com, yao.jin@linux.intel.com,
robert.richter@amd.com, kim.phillips@amd.com,
maddy@linux.ibm.com, ravi.bangoria@linux.ibm.com,
Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Subject: [RFC 03/11] powerpc/perf: Arch specific definitions for pipeline
Date: Mon, 2 Mar 2020 10:53:47 +0530 [thread overview]
Message-ID: <20200302052355.36365-4-ravi.bangoria@linux.ibm.com> (raw)
In-Reply-To: <20200302052355.36365-1-ravi.bangoria@linux.ibm.com>
From: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Create powerpc specific definitions for pipeline hazard and stalls.
This information is available in SIER register on powerpc. Current
definitions are based on IBM PowerPC SIER specification available
in ISA[1] and Performance Monitor Unit User’s Guide[2].
[1]: Book III, Section 9.4.10:
https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0
[2]: https://wiki.raptorcs.com/w/images/6/6b/POWER9_PMU_UG_v12_28NOV2018_pub.pdf#G9.1106986
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com>
---
.../include/uapi/asm/perf_pipeline_haz.h | 80 +++++++++++++++++++
1 file changed, 80 insertions(+)
create mode 100644 arch/powerpc/include/uapi/asm/perf_pipeline_haz.h
diff --git a/arch/powerpc/include/uapi/asm/perf_pipeline_haz.h b/arch/powerpc/include/uapi/asm/perf_pipeline_haz.h
new file mode 100644
index 000000000000..de8857ec31dd
--- /dev/null
+++ b/arch/powerpc/include/uapi/asm/perf_pipeline_haz.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#ifndef _UAPI_ASM_POWERPC_PERF_PIPELINE_HAZ_H
+#define _UAPI_ASM_POWERPC_PERF_PIPELINE_HAZ_H
+
+enum perf_inst_type {
+ PERF_HAZ__ITYPE_LOAD = 1,
+ PERF_HAZ__ITYPE_STORE,
+ PERF_HAZ__ITYPE_BRANCH,
+ PERF_HAZ__ITYPE_FP,
+ PERF_HAZ__ITYPE_FX,
+ PERF_HAZ__ITYPE_CR_OR_SC,
+};
+
+enum perf_inst_cache {
+ PERF_HAZ__ICACHE_L1_HIT = 1,
+ PERF_HAZ__ICACHE_L2_HIT,
+ PERF_HAZ__ICACHE_L3_HIT,
+ PERF_HAZ__ICACHE_L3_MISS,
+};
+
+enum perf_pipeline_stage {
+ PERF_HAZ__PIPE_STAGE_IFU = 1,
+ PERF_HAZ__PIPE_STAGE_IDU,
+ PERF_HAZ__PIPE_STAGE_ISU,
+ PERF_HAZ__PIPE_STAGE_LSU,
+ PERF_HAZ__PIPE_STAGE_BRU,
+ PERF_HAZ__PIPE_STAGE_FXU,
+ PERF_HAZ__PIPE_STAGE_FPU,
+ PERF_HAZ__PIPE_STAGE_VSU,
+ PERF_HAZ__PIPE_STAGE_OTHER,
+};
+
+enum perf_haz_bru_reason {
+ PERF_HAZ__HAZ_BRU_MPRED_DIR = 1,
+ PERF_HAZ__HAZ_BRU_MPRED_TA,
+};
+
+enum perf_haz_isu_reason {
+ PERF_HAZ__HAZ_ISU_SRC = 1,
+ PERF_HAZ__HAZ_ISU_COL = 1,
+};
+
+enum perf_haz_lsu_reason {
+ PERF_HAZ__HAZ_LSU_ERAT_MISS = 1,
+ PERF_HAZ__HAZ_LSU_LMQ,
+ PERF_HAZ__HAZ_LSU_LHS,
+ PERF_HAZ__HAZ_LSU_MPRED,
+ PERF_HAZ__HAZ_DERAT_MISS,
+ PERF_HAZ__HAZ_LSU_LMQ_DERAT_MISS,
+ PERF_HAZ__HAZ_LSU_LHS_DERAT_MISS,
+ PERF_HAZ__HAZ_LSU_MPRED_DERAT_MISS,
+};
+
+enum perf_stall_lsu_reason {
+ PERF_HAZ__STALL_LSU_DCACHE_MISS = 1,
+ PERF_HAZ__STALL_LSU_LD_FIN,
+ PERF_HAZ__STALL_LSU_ST_FWD,
+ PERF_HAZ__STALL_LSU_ST,
+};
+
+enum perf_stall_fxu_reason {
+ PERF_HAZ__STALL_FXU_MC = 1,
+ PERF_HAZ__STALL_FXU_FC,
+};
+
+enum perf_stall_bru_reason {
+ PERF_HAZ__STALL_BRU_FIN_MPRED = 1,
+ PERF_HAZ__STALL_BRU_FC,
+};
+
+enum perf_stall_vsu_reason {
+ PERF_HAZ__STALL_VSU_MC = 1,
+ PERF_HAZ__STALL_VSU_FC,
+};
+
+enum perf_stall_other_reason {
+ PERF_HAZ__STALL_NTC,
+};
+
+#endif /* _UAPI_ASM_POWERPC_PERF_PIPELINE_HAZ_H */
--
2.21.1
next prev parent reply other threads:[~2020-03-02 5:24 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-02 5:23 [RFC 00/11] perf: Enhancing perf to export processor hazard information Ravi Bangoria
2020-03-02 5:23 ` [RFC 01/11] powerpc/perf: Simplify ISA207_SIER macros Ravi Bangoria
2020-03-02 5:23 ` [RFC 02/11] perf/core: Data structure to present hazard data Ravi Bangoria
2020-03-02 9:55 ` Peter Zijlstra
2020-03-02 14:23 ` maddy
2020-03-02 14:48 ` Mark Rutland
2020-03-03 14:32 ` Ravi Bangoria
2020-03-02 14:54 ` Mark Rutland
2020-03-03 14:31 ` Ravi Bangoria
2020-03-02 5:23 ` Ravi Bangoria [this message]
2020-03-02 5:23 ` [RFC 04/11] powerpc/perf: Arch support to expose Hazard data Ravi Bangoria
2020-03-02 5:23 ` [RFC 05/11] perf tools: Enable record and script to record and show hazard data Ravi Bangoria
2020-03-02 5:23 ` [RFC 06/11] perf hists: Make a room for hazard info in struct hist_entry Ravi Bangoria
2020-03-02 5:23 ` [RFC 07/11] perf hazard: Functions to convert generic hazard data to arch specific string Ravi Bangoria
2020-03-02 5:23 ` [RFC 08/11] perf report: Enable hazard mode Ravi Bangoria
2020-03-02 5:23 ` [RFC 09/11] perf annotate: Introduce type for annotation_line Ravi Bangoria
2020-03-02 5:23 ` [RFC 10/11] perf annotate: Preparation for hazard Ravi Bangoria
2020-03-02 5:23 ` [RFC 11/11] perf annotate: Show hazard data in tui mode Ravi Bangoria
2020-03-02 10:13 ` [RFC 00/11] perf: Enhancing perf to export processor hazard information Peter Zijlstra
2020-03-02 20:21 ` Stephane Eranian
2020-03-02 22:25 ` Kim Phillips
2020-03-05 4:46 ` Ravi Bangoria
2020-03-05 22:06 ` Kim Phillips
2020-03-11 16:00 ` Ravi Bangoria
2020-03-12 22:38 ` Kim Phillips
2020-03-17 6:50 ` maddy
2020-03-18 17:35 ` Kim Phillips
2020-03-19 11:22 ` Michael Ellerman
2020-03-26 10:19 ` maddy
2020-03-26 19:48 ` Kim Phillips
2020-04-20 7:09 ` Madhavan Srinivasan
2020-04-27 7:18 ` Madhavan Srinivasan
2020-03-05 4:28 ` maddy
2020-03-03 1:33 ` Andi Kleen
2020-03-05 5:06 ` Ravi Bangoria
2020-03-02 21:08 ` Paul Clarke
2020-03-05 5:06 ` Ravi Bangoria
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