From: guoren@kernel.org
To: paul.walmsley@sifive.com, palmer@dabbelt.com, Anup.Patel@wdc.com,
greentime.hu@sifive.com
Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org,
arnd@arndb.de, linux-csky@vger.kernel.org,
linux-riscv@lists.infradead.org,
Guo Ren <guoren@linux.alibaba.com>,
Dave Martin <Dave.Martin@arm.com>
Subject: [RFC PATCH V3 03/11] riscv: Extending cpufeature.c to detect V-extension
Date: Sun, 8 Mar 2020 17:49:46 +0800 [thread overview]
Message-ID: <20200308094954.13258-4-guoren@kernel.org> (raw)
In-Reply-To: <20200308094954.13258-1-guoren@kernel.org>
From: Guo Ren <guoren@linux.alibaba.com>
From: Guo Ren <ren_guo@c-sky.com>
Current cpufeature.c doesn't support detecting V-extension, because
"rv64" also contain a 'v' letter and we need to skip it.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
arch/riscv/include/uapi/asm/hwcap.h | 1 +
arch/riscv/kernel/cpufeature.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/asm/hwcap.h
index dee98ee28318..a913e9a38819 100644
--- a/arch/riscv/include/uapi/asm/hwcap.h
+++ b/arch/riscv/include/uapi/asm/hwcap.h
@@ -21,5 +21,6 @@
#define COMPAT_HWCAP_ISA_F (1 << ('F' - 'A'))
#define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A'))
#define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A'))
+#define COMPAT_HWCAP_ISA_V (1 << ('V' - 'A'))
#endif /* _UAPI_ASM_RISCV_HWCAP_H */
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index a5ad00043104..c8527d770c98 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -30,6 +30,7 @@ void riscv_fill_hwcap(void)
isa2hwcap['f'] = isa2hwcap['F'] = COMPAT_HWCAP_ISA_F;
isa2hwcap['d'] = isa2hwcap['D'] = COMPAT_HWCAP_ISA_D;
isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C;
+ isa2hwcap['v'] = isa2hwcap['V'] = COMPAT_HWCAP_ISA_V;
elf_hwcap = 0;
@@ -44,7 +45,8 @@ void riscv_fill_hwcap(void)
continue;
}
- for (i = 0; i < strlen(isa); ++i)
+ /* Skip rv64/rv32 to support v/V:vector */
+ for (i = 4; i < strlen(isa); ++i)
this_hwcap |= isa2hwcap[(unsigned char)(isa[i])];
/*
--
2.17.0
next prev parent reply other threads:[~2020-03-08 9:53 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-08 9:49 [RFC PATCH V3 00/11] riscv: Add vector ISA support guoren
2020-03-08 9:49 ` [RFC PATCH V3 01/11] riscv: Separate patch for cflags and aflags guoren
2020-03-08 9:49 ` [RFC PATCH V3 02/11] riscv: Rename __switch_to_aux -> fpu guoren
2020-03-08 9:49 ` guoren [this message]
2020-03-08 9:49 ` [RFC PATCH V3 04/11] riscv: Add CSR defines related to VECTOR extension guoren
2020-03-08 9:49 ` [RFC PATCH V3 05/11] riscv: Add vector feature to compile guoren
2020-03-08 9:49 ` [RFC PATCH V3 06/11] riscv: Add has_vector detect guoren
2020-03-08 9:49 ` [RFC PATCH V3 07/11] riscv: Reset vector register guoren
2020-03-08 9:49 ` [RFC PATCH V3 08/11] riscv: Add vector struct and assembler definitions guoren
2020-03-08 9:49 ` [RFC PATCH V3 09/11] riscv: Add task switch support for VECTOR guoren
2020-03-08 9:49 ` [RFC PATCH V3 10/11] riscv: Add ptrace support guoren
2020-03-08 9:49 ` [RFC PATCH V3 11/11] riscv: Add sigcontext save/restore guoren
2020-03-09 3:41 ` [RFC PATCH V3 00/11] riscv: Add vector ISA support Greentime Hu
2020-03-09 10:27 ` LIU Zhiwei
2020-03-10 8:54 ` Greentime Hu
2020-03-10 9:19 ` Greentime Hu
2020-03-12 3:14 ` LIU Zhiwei
2020-03-23 4:00 ` Greentime Hu
2020-03-24 3:41 ` Guo Ren
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