From: guoren@kernel.org
To: paul.walmsley@sifive.com, palmer@dabbelt.com, Anup.Patel@wdc.com,
greentime.hu@sifive.com
Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org,
arnd@arndb.de, linux-csky@vger.kernel.org,
linux-riscv@lists.infradead.org,
Guo Ren <guoren@linux.alibaba.com>,
Dave Martin <Dave.Martin@arm.com>
Subject: [RFC PATCH V3 05/11] riscv: Add vector feature to compile
Date: Sun, 8 Mar 2020 17:49:48 +0800 [thread overview]
Message-ID: <20200308094954.13258-6-guoren@kernel.org> (raw)
In-Reply-To: <20200308094954.13258-1-guoren@kernel.org>
From: Guo Ren <guoren@linux.alibaba.com>
This patch add a config option which could enable assembler's
vector feature.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
---
arch/riscv/Kconfig | 9 +++++++++
arch/riscv/Makefile | 1 +
2 files changed, 10 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 73f029eae0cc..c36589c85700 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -288,6 +288,15 @@ config FPU
If you don't know what to do here, say Y.
+config VECTOR
+ bool "VECTOR support"
+ default n
+ help
+ Say N here if you want to disable all vector related procedure
+ in the kernel.
+
+ If you don't know what to do here, say Y.
+
endmenu
menu "Kernel features"
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 6d09b53cf106..071eb1148e01 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -44,6 +44,7 @@ riscv-march-aflags-$(CONFIG_ARCH_RV32I) := rv32ima
riscv-march-aflags-$(CONFIG_ARCH_RV64I) := rv64ima
riscv-march-aflags-$(CONFIG_FPU) := $(riscv-march-aflags-y)fd
riscv-march-aflags-$(CONFIG_RISCV_ISA_C) := $(riscv-march-aflags-y)c
+riscv-march-aflags-$(CONFIG_VECTOR) := $(riscv-march-aflags-y)v
KBUILD_CFLAGS += -march=$(riscv-march-cflags-y)
KBUILD_AFLAGS += -march=$(riscv-march-aflags-y)
--
2.17.0
next prev parent reply other threads:[~2020-03-08 9:54 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-08 9:49 [RFC PATCH V3 00/11] riscv: Add vector ISA support guoren
2020-03-08 9:49 ` [RFC PATCH V3 01/11] riscv: Separate patch for cflags and aflags guoren
2020-03-08 9:49 ` [RFC PATCH V3 02/11] riscv: Rename __switch_to_aux -> fpu guoren
2020-03-08 9:49 ` [RFC PATCH V3 03/11] riscv: Extending cpufeature.c to detect V-extension guoren
2020-03-08 9:49 ` [RFC PATCH V3 04/11] riscv: Add CSR defines related to VECTOR extension guoren
2020-03-08 9:49 ` guoren [this message]
2020-03-08 9:49 ` [RFC PATCH V3 06/11] riscv: Add has_vector detect guoren
2020-03-08 9:49 ` [RFC PATCH V3 07/11] riscv: Reset vector register guoren
2020-03-08 9:49 ` [RFC PATCH V3 08/11] riscv: Add vector struct and assembler definitions guoren
2020-03-08 9:49 ` [RFC PATCH V3 09/11] riscv: Add task switch support for VECTOR guoren
2020-03-08 9:49 ` [RFC PATCH V3 10/11] riscv: Add ptrace support guoren
2020-03-08 9:49 ` [RFC PATCH V3 11/11] riscv: Add sigcontext save/restore guoren
2020-03-09 3:41 ` [RFC PATCH V3 00/11] riscv: Add vector ISA support Greentime Hu
2020-03-09 10:27 ` LIU Zhiwei
2020-03-10 8:54 ` Greentime Hu
2020-03-10 9:19 ` Greentime Hu
2020-03-12 3:14 ` LIU Zhiwei
2020-03-23 4:00 ` Greentime Hu
2020-03-24 3:41 ` Guo Ren
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