From: peng.fan@nxp.com
To: shawnguo@kernel.org, s.hauer@pengutronix.de,
leonard.crestez@nxp.com, sboyd@kernel.org, abel.vesa@nxp.com
Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Anson.Huang@nxp.com,
daniel.baluta@nxp.com, aford173@gmail.com, ping.bai@nxp.com,
jun.li@nxp.com, l.stach@pengutronix.de, andrew.smirnov@gmail.com,
agx@sigxcpu.org, angus@akkea.ca, heiko@sntech.de,
fugang.duan@nxp.com, linux-clk@vger.kernel.org,
Peng Fan <peng.fan@nxp.com>
Subject: [PATCH 06/10] clk: imx8m: migrate A53 clk root to use composite core
Date: Thu, 12 Mar 2020 17:01:28 +0800 [thread overview]
Message-ID: <1584003692-25523-7-git-send-email-peng.fan@nxp.com> (raw)
In-Reply-To: <1584003692-25523-1-git-send-email-peng.fan@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
Migrate A53 clk root to use composite core clk type. It
will simplify code and make it easy to use composite
specific mux operation.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk-imx8mm.c | 6 +++---
drivers/clk/imx/clk-imx8mn.c | 6 +++---
drivers/clk/imx/clk-imx8mq.c | 6 +++---
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 5435042a06e3..12443e06f329 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -416,9 +416,9 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
return PTR_ERR(base);
/* Core Slice */
- hws[IMX8MM_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels));
- hws[IMX8MM_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28);
- hws[IMX8MM_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
+ hws[IMX8MM_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mm_a53_sels, base + 0x8000);
+ hws[IMX8MM_CLK_A53_CG] = hws[IMX8MM_CLK_A53_DIV];
+ hws[IMX8MM_CLK_A53_SRC] = hws[IMX8MM_CLK_A53_DIV];
hws[IMX8MM_CLK_M4_CORE] = imx8m_clk_hw_composite_core("arm_m4_core", imx8mm_m4_sels, base + 0x8080);
hws[IMX8MM_CLK_VPU_CORE] = imx8m_clk_hw_composite_core("vpu_core", imx8mm_vpu_sels, base + 0x8100);
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 6cac6ca03e12..bd3759b4afd0 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -413,9 +413,9 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
}
/* CORE */
- hws[IMX8MN_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels));
- hws[IMX8MN_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28);
- hws[IMX8MN_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
+ hws[IMX8MN_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mn_a53_sels, base + 0x8000);
+ hws[IMX8MN_CLK_A53_SRC] = hws[IMX8MN_CLK_A53_DIV];
+ hws[IMX8MN_CLK_A53_CG] = hws[IMX8MN_CLK_A53_DIV];
hws[IMX8MN_CLK_GPU_CORE] = imx8m_clk_hw_composite_core("gpu_core", imx8mn_gpu_core_sels, base + 0x8180);
hws[IMX8MN_CLK_GPU_SHADER] = imx8m_clk_hw_composite_core("gpu_shader", imx8mn_gpu_shader_sels, base + 0x8200);
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 201c7bbb201f..91309ff65441 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -405,9 +405,9 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
return PTR_ERR(base);
/* CORE */
- hws[IMX8MQ_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels));
- hws[IMX8MQ_CLK_A53_CG] = imx_clk_hw_gate3_flags("arm_a53_cg", "arm_a53_src", base + 0x8000, 28, CLK_IS_CRITICAL);
- hws[IMX8MQ_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
+ hws[IMX8MQ_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mq_a53_sels, base + 0x8000);
+ hws[IMX8MQ_CLK_A53_CG] = hws[IMX8MQ_CLK_A53_DIV];
+ hws[IMX8MQ_CLK_A53_SRC] = hws[IMX8MQ_CLK_A53_DIV];
hws[IMX8MQ_CLK_M4_CORE] = imx8m_clk_hw_composite_core("arm_m4_core", imx8mq_arm_m4_sels, base + 0x8080);
hws[IMX8MQ_CLK_VPU_CORE] = imx8m_clk_hw_composite_core("vpu_core", imx8mq_vpu_sels, base + 0x8100);
--
2.16.4
next prev parent reply other threads:[~2020-03-12 9:08 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-12 9:01 [PATCH 00/10] clk: imx: fixes and improve for i.MX8M peng.fan
2020-03-12 9:01 ` [PATCH 01/10] arm64: dts: imx8m: assign clocks for A53 peng.fan
2020-03-12 9:01 ` [PATCH 02/10] clk: imx8m: drop clk_hw_set_parent " peng.fan
2020-03-12 9:01 ` [PATCH 03/10] clk: imx: imx8mp: fix pll mux bit peng.fan
2020-03-12 9:01 ` [PATCH 04/10] clk: imx8mp: Define gates for pll1/2 fixed dividers peng.fan
2020-03-12 9:01 ` [PATCH 05/10] clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code peng.fan
2020-03-12 9:01 ` peng.fan [this message]
2020-03-12 9:01 ` [PATCH 07/10] clk: imx: add mux ops for i.MX8M composite clk peng.fan
2020-03-12 9:01 ` [PATCH 08/10] clk: imx: add imx8m_clk_hw_composite_bus peng.fan
2020-03-12 9:01 ` [PATCH 09/10] clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice peng.fan
2020-03-12 9:01 ` [PATCH 10/10] clk: imx8mp: mark memrepair clock as critical peng.fan
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