[RFC] clk: vc5: Add bindings for output configurations

From: Adam Ford <aford173@gmail.com>
To: devicetree@vger.kernel.org
Cc: aford@beaconembedded.com, charles.stevens@logicpd.com,
	Adam Ford <aford173@gmail.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [RFC] clk: vc5: Add bindings for output configurations
Date: Thu, 26 Mar 2020 16:32:51 -0500	[thread overview]
Message-ID: <20200326213251.54457-1-aford173@gmail.com> (raw)

The Versaclock can be purchased in a non-programmed configuration.
If that is the case, the driver needs to configure the chip to
output the correct signal type, voltage and slew.

This RFC is proposing an additional binding to allow non-programmed
chips to be configured beyond their default configuration.

Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
index 05a245c9df08..4bc46ed9ba4a 100644
--- a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
+++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
@@ -30,6 +30,25 @@ Required properties:
 		- 5p49v5933 and
 		- 5p49v5935: (optional) property not present or "clkin".
 
+For all output ports, an option child node can be used to specify:
+
+- mode: can be one of
+		  - LVPECL: Low-voltage positive/psuedo emitter-coupled logic
+		  - CMOS
+		  - HCSL 
+		  - LVDS: Low voltage differential signal
+
+- voltage-level:  can be one of the following microvolts
+		  - 1800000
+		  - 2500000
+		  - 3300000
+-  slew: Percent of normal, can be one of 
+		  - P80 
+		  - P85
+		  - P90
+		  - P100 
+
+
 ==Mapping between clock specifier and physical pins==
 
 When referencing the provided clock in the DT using phandle and
@@ -62,6 +81,8 @@ clock specifier, the following mapping applies:
 
 ==Example==
 
+#include <dt-bindings/versaclock.h>
+
 /* 25MHz reference crystal */
 ref25: ref25m {
 	compatible = "fixed-clock";
@@ -80,6 +101,13 @@ i2c-master-node {
 		/* Connect XIN input to 25MHz reference */
 		clocks = <&ref25m>;
 		clock-names = "xin";
+
+		ports@1 {
+			reg = <1>;
+			mode = <CMOS>;
+			pwr_sel = <1800000>;
+			slew = <P80>;
+		};
 	};
 };
 
-- 
2.25.1

