From: Manish Narani <manish.narani@xilinx.com>
To: ulf.hansson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com,
adrian.hunter@intel.com, michal.simek@xilinx.com
Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, git@xilinx.com,
Manish Narani <manish.narani@xilinx.com>
Subject: [PATCH v2 1/4] dt-bindings: mmc: arasan: Document 'xlnx,versal-8.9a' controller
Date: Mon, 30 Mar 2020 11:11:16 +0530 [thread overview]
Message-ID: <1585546879-91037-2-git-send-email-manish.narani@xilinx.com> (raw)
In-Reply-To: <1585546879-91037-1-git-send-email-manish.narani@xilinx.com>
Add documentation for 'xlnx,versal-8.9a' SDHCI controller followed by
example.
Signed-off-by: Manish Narani <manish.narani@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/mmc/arasan,sdhci.txt | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index 428685eb2ded..630fe707f5c4 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -18,6 +18,9 @@ Required Properties:
- "xlnx,zynqmp-8.9a": ZynqMP SDHCI 8.9a PHY
For this device it is strongly suggested to include clock-output-names and
#clock-cells.
+ - "xlnx,versal-8.9a": Versal SDHCI 8.9a PHY
+ For this device it is strongly suggested to include clock-output-names and
+ #clock-cells.
- "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY
Note: This binding has been deprecated and moved to [5].
- "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel LGM eMMC PHY
@@ -104,6 +107,18 @@ Example:
clk-phase-sd-hs = <63>, <72>;
};
+ sdhci: mmc@f1040000 {
+ compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
+ interrupt-parent = <&gic>;
+ interrupts = <0 126 4>;
+ reg = <0x0 0xf1040000 0x0 0x10000>;
+ clocks = <&clk200>, <&clk200>;
+ clock-names = "clk_xin", "clk_ahb";
+ clock-output-names = "clk_out_sd0", "clk_in_sd0";
+ #clock-cells = <1>;
+ clk-phase-sd-hs = <132>, <60>;
+ };
+
emmc: sdhci@ec700000 {
compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
reg = <0xec700000 0x300>;
--
2.17.1
next prev parent reply other threads:[~2020-03-30 5:41 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-30 5:41 [PATCH v2 0/4] Add support for Xilinx Versal SDHCI in Arasan driver Manish Narani
2020-03-30 5:41 ` Manish Narani [this message]
2020-03-30 5:41 ` [PATCH v2 2/4] sdhci: arasan: Add support for Versal Tap Delays Manish Narani
2020-04-02 10:11 ` Adrian Hunter
2020-03-30 5:41 ` [PATCH v2 3/4] mmc: sdhci-of-arasan: Modify clock operations handling Manish Narani
2020-04-02 10:10 ` Adrian Hunter
2020-04-06 13:55 ` Manish Narani
2020-03-30 5:41 ` [PATCH v2 4/4] mmc: sdhci-of-arasan: Fix kernel-doc warnings Manish Narani
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