From: Thierry Reding <thierry.reding@gmail.com>
To: Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Thierry Reding <thierry.reding@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Jon Hunter <jonathanh@nvidia.com>,
devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v2 1/7] dt-bindings: timer: Add bindings for NVIDIA Tegra186 timers
Date: Wed, 1 Apr 2020 00:19:08 +0200 [thread overview]
Message-ID: <20200331221914.2966407-2-thierry.reding@gmail.com> (raw)
In-Reply-To: <20200331221914.2966407-1-thierry.reding@gmail.com>
From: Thierry Reding <treding@nvidia.com>
The NVIDIA Tegra186 SoC contains an IP block that provides a register
interface for ten timers with a 29-bit counter that can generate one-
shot, periodic or watchdog interrupts.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- add required properties section
- add additionalProperties: false
- do not show status in example
.../bindings/timer/nvidia,tegra186-timer.yaml | 61 +++++++++++++++++++
1 file changed, 61 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml
diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml
new file mode 100644
index 000000000000..d722cd267bf9
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra186 timers
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jonathan Hunter <jonathanh@nvidia.com>
+
+description: |
+ The Tegra186 timer provides ten 29-bit timer counters and one 32-bit TSC
+ (timestamp counter). The timers run at either a fixed 1 MHz clock rate
+ derived from the oscillator clock. Each timer can be programmed to raise
+ one-shot, periodic, or watchdog interrupts.
+
+properties:
+ compatible:
+ oneOf:
+ - description: NVIDIA Tegra186
+ items:
+ - const: nvidia,tegra186-timer
+
+ - description: NVIDIA Tegra194
+ items:
+ - const: nvidia,tegra194-timer
+ - const: nvidia,tegra186-timer
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 10
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ timer@3010000 {
+ compatible = "nvidia,tegra186-timer";
+ reg = <0x03010000 0x000e0000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
--
2.24.1
next prev parent reply other threads:[~2020-03-31 22:19 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-31 22:19 [PATCH v2 0/7] clocksource: Add NVIDIA Tegra186 timers support Thierry Reding
2020-03-31 22:19 ` Thierry Reding [this message]
2020-03-31 22:19 ` [PATCH v2 2/7] clocksource: Add " Thierry Reding
2020-04-03 16:14 ` Dmitry Osipenko
2020-04-03 20:13 ` Thierry Reding
2020-04-03 16:24 ` Dmitry Osipenko
2020-04-03 20:14 ` Thierry Reding
2020-04-03 16:33 ` Dmitry Osipenko
2020-04-03 20:15 ` Thierry Reding
2020-03-31 22:19 ` [PATCH v2 3/7] arm64: tegra: Order nodes by unit-address on Tegra194 Thierry Reding
2020-03-31 22:19 ` [PATCH v2 4/7] arm64: tegra: Add native timer support on Tegra186 Thierry Reding
2020-03-31 22:19 ` [PATCH v2 5/7] arm64: tegra: Enable native timers on Jetson TX2 Thierry Reding
2020-03-31 22:19 ` [PATCH v2 6/7] arm64: tegra: Add native timer support on Tegra194 Thierry Reding
2020-03-31 22:19 ` [PATCH v2 7/7] arm64: tegra: Enable native timers on Jetson AGX Xavier Thierry Reding
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